CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 13

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. CYNSE70128 Signal Description (continued)
5.0
If the CLK_MODE pin is LOW, CYNSE70128 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X
and generate a CLK, as shown in Figure 5-1. The CYNSE70128 uses CLK2X and CLK for internal operations. Also noted on
these figures are cycles A and B. Cycle A ends on the rising edge of CLK2X, when PHS_L is high. Cycle B ends on the falling
edge of the CLK2X when PHS_L is low. Valid data for cycle A must be available for the NSE at the end of cycle A. Valid data for
cycle B must be available for the NSE at the end of cycle B. PHS_L has setup and hold times requirements with respect to CLK2X.
The setup and hold time requirements can be referred to in Sections 17.0 AC Timing Waveforms.
If the CLK_MODE pin is HIGH, CYNSE70128 receives the CLK1X only. CYNSE70128 uses an internal PLL to double the
frequency of CLK1X and then divides that clock by two to generate a CLK for internal operations, as shown in Figure 5-2.
Notes:
Document #: 38-02040 Rev. *F
Device Identification
Supplies
Test Access Port
6.
7.
Pin Name
FULO[1:0]
TRST_L
Any reference to “CLK” cycles means one CLK cycle.
For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode. For a timing diagram in CLK1X mode, the
following substitution can be made (see Figure 5-3).
ID[4:0]
FULL
V
TDO
TMS
TCK
V
TDI
DDQ
DD
Clocks
Type
Pin
n/a
n/a
[6]
O
O
T
I
I
I
I
I
Input Data
[1]
CLK1X
CLK
CLK2X
PHS_L
Full Out:
to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0] in the data array indicates
whether the entry is full (1) or empty (0).This signal is asserted if all bits in the data array are ones.
(Refer to ”Depth-Cascading” on page 102 for information on how to generate the FULL flag.)
Full Flag:
Device Identification:
00000 and goes up to 11110. 11111 is reserved for a special broadcast address that selects all cascaded
NSEs in the system. On a broadcast read-only, the device with the LDEV bit set to 1 responds.
Chip core supply:
Chip I/O supply:
Test access port’s test data in.
Test access port’s test clock.
Test access port’s test data out.
Test access port’s test mode select.
Test access port’s reset.
CLK
FULO[1] and FULO[0] are the same logical signal. One of these two signals must be connected
Figure 5-1. CYNSE70128 Clocks (CLK2X and PHS_L)
When asserted, this signal indicates that the table of multiple depth-cascaded devices is full.
“Cycle A End”
2.5V or 3.3V (CYNSE70128-XXX)
Figure 5-2. CYNSE70128 Clocks (CLK1X)
1.5V. (1.65V for search rates greater than 83 msps.)
The binary-encoded device identification for a depth-cascaded system starts at
A
“Cycle B End”
B
Pin Description
CYNSE70128
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