CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 29

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Note
and odd pair of GMRs selected for the compare must be programmed with the same value.
The logical 72-bit Search operation is shown in Figure 10-7. The entire table consisting of 72-bit entries is compared to a 72-bit
word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective
GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the
command’s cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both
even and odd comparand register pairs selected by the Comparand Register Index in the command’s cycle B. In a ×72 configu-
ration, only the even comparand register can be subsequently used by the Learn command. The word K (presented on the DQ
bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching
entry’s location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see “SRAM
Addressing” on page 105).
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit
searches in ×72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-10.
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle
The latency of a Search from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-11.
Table 10-11. Shift OF SSF and SSV from SADR
Document #: 38-02040 Rev. *F
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 8 for information on SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared.
. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. The even
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
110
111
Comparand Register (odd)
Comparand Register (even)
71
K
K
Figure 10-7. x72 Table with One Device
Max Table Size
1984K × 72 bits
512K × 72 bits
64K × 72 bits
0
Location
address
65535
0
1
2
3
L
CFG = 0000000000000000
71
71
Number of CLK Cycles
(288-bit configuration)
GMR
K
0
1
2
3
4
5
6
7
Latency in CLK Cycles
0
0
(First matching entry)
4
5
6
CYNSE70128
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