W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 13

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

This is the high byte of the new additional 16-bit data pointer that has been added to the W77C32.
The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The
instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not
required they can be used as conventional register locations by the user.
Data Pointer Select
DPS.0: This bit is used to select either the DPL, DPH pair or the DPL1, DPH1 pair as the active Data
DPS.1-7: These bits are reserved, but will read 0.
Power Control
SMOD: This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7)
GF1-0:
PD:
IDL:
Timer Control
TF1:
TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
TF0:
TR0: Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL, DPH will be selected.
Setting this bit causes the W77C32 to go into the POWER DOWN mode. In this mode all the
clocks are stopped and program execution is frozen.
Setting this bit causes the W77C32 to go into the IDLE mode. In this mode the clocks to the
CPU are stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then
SCON.7(SCON1.7) acts as per the standard 8052 function.
These two bits are general purpose user flags.
Mnemonic: DPS
Mnemonic: PCON
Mnemonic: TCON
Bit:
Bit:
Bit:
SM0D
TF1
7
7
7
-
SMOD0
TR1
6
6
6
-
TF0
5
-
5
5
-
- 13 -
TR0
4
-
4
4
-
Publication Release Date: December 20, 2005
GF1
IE1
3
3
3
-
W77C32/W77C032
Address: 86h
Address: 87h
Address: 88h
GF0
2
IT
2
2
-
PD
IE0
1
1
1
-
Revision A5
DPS.0
IDL
0
IT
0
0