W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 17

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.1 External Interrupt Flag
IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5 .
IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT5 .
IE2: External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
XT/ RG RG: Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system
RGMD: RC Mode Status. This bit indicates the current clock source of microcontroller. When cleared,
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down
Serial Port Control
SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines
SM1: Serial port Mode bit 1:
clock source. Clearing this bit selects the on-chip RC oscillator as clock source.
XTUP(STATUS.4) must be set to 1 and XTOFF (PMR.3) must be cleared before this bit can
be set. Attempts to set this bit without obeying these conditions will be ignored. This bit is set
to 1 after a power-on reset and unchanged by other forms of reset.
CPU is operating from the external crystal or oscillator. When set, CPU is operating from the
on-chip RC oscillator. This bit is cleared to 0 after a power-on reset and unchanged by other
forms of reset.
Mode. Setting this bit allows device operating from RC oscillator when a resume from Power
Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator
has warmed-up following a resume from Power Down Mode. This bit is cleared to 0 after a
power-on reset and unchanged by other forms of reset.
whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used
as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in
software to clear the FE condition.
SM0 SM1 Mode Description
0
0
1
1
Mnemonic: EXIF
Mnemonic: SCON
0
1
0
1
Bit:
Bit:
0
1
2
3
SM0/FE
IE5
7
7
Synchronous
Asynchronous
Asynchronous
Asynchronous
IE4
SM1
6
6
IE3
SM2
5
- 17 -
5
Length
10
11
11
8
REN
IE2
4
4
Publication Release Date: December 20, 2005
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
XT/RG
TB8
3
3
W77C32/W77C032
Address: 91h
Address: 98h
RGMD
RB8
2
2
RGSL
TI
1
1
Revision A5
BGS
RI
0
0