W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 53

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

13.1.2 Mode 0
In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode
we have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx.
The upper 3 bits of TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx
moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves
from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if
TRx is set and either GATE = 0 or INTx = 1. When C/ T is set to 0, then it will count clock cycles, and
if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1.
When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer
overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when
used as a timer, the time-base may be either clock cycles/12 or clock cycles/4 as selected by the bits
TxM of the CKCON SFR.
13.1.3 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
13.1.4 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count
register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx
bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues
from here. The reload operation leaves the contents of the THx register unchanged. Counting is
enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1,
mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
div. by 4
div. by 64
div. by 1024 osc/256
Mode
Clock Source
(GATE = TMOD.7)
(TR1 = TCON.6)
GATE = TMOD.3
TR0 = TCON.4
(T1 = P3.5)
(INT1 = P3.3)
T0 = P3.4
INT0 = P3.2
osc/1
osc/16
input
(T1M = CKCON.4)
T0M = CKCON.3
1/12
1/4
1
0
Figure 11: Timer/Counter Mode 0 & Mode 1
(C/T = TMOD.6)
C/T = TMOD.2
0
1
- 53 -
0
Timer 1 functions are shown in brackets
(TL1)
Publication Release Date: December 20, 2005
TL0
4
(M1,M0 = TMOD.5,TMOD.4)
M1,M0 = TMOD.1,TMOD.0
7
W77C32/W77C032
(TF1)
TFx
TF0
00
01
0
Interrupt
(TH1)
TH0
Revision A5
7