AM29DL323DB-120EI Spansion Inc., AM29DL323DB-120EI Datasheet - Page 11

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AM29DL323DB-120EI

Manufacturer Part Number
AM29DL323DB-120EI
Description
Manufacturer
Spansion Inc.
Datasheet

Specifications of AM29DL323DB-120EI

Cell Type
NOR
Density
32Mb
Access Time (max)
120ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
22/21Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
3/8.5 to 9.5V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
4M/2M
Supply Current
16mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM29DL323DB-120EI
Manufacturer:
AMD
Quantity:
20 000
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
d re s s a c ce s s ti m in g s pr ov id e n ew d at a w he n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
10
CC5
Am29DL322D
Am29DL323D
Am29DL324D
Part Number
IL
in the DC Characteristics table represents the
Device
but not within V
Megabits
SS
16 Mbit
4 Mbit
8 Mbit
±0.3 V, the standby current will
CC4
SS
). If RESET# is held
±0.3 V, the device
thirty-one 64 Kbyte/32 Kword
fifteen 64 Kbyte/32 Kword
seven 64 Kbyte/32 Kword
Table 2. Device Bank Divisions
Bank 1
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
Am29DL322D/323D/324D
Sector Sizes
RP
,
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V
I
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 14 for the
timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
CC4
in the DC Characteristics table represents the
READY
Megabits
28 Mbit
24 Mbit
16 Mbit
(during Embedded Algorithms). The
IH
READY
Bank 2
IH
, output from the device is
.
64 Kbyte/32 Kword
64 Kbyte/32 Kword
64 Kbyte/32 Kword
Sector Sizes
December 13, 2005
(not during Embed-
Forty-eight
Thirty-two
Fifty-six
RH
after

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