MD3331-D64-V3-X SanDisk, MD3331-D64-V3-X Datasheet - Page 44

• Manufacturer Part Number: MD3331-D64-V3-X
• Manufacturer: SanDisk
• Type: Flash Diskr

Specifications of MD3331-D64-V3-X

• Density: 64MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: FBGA
• Mounting: Surface Mount
• Pin Count: 69
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Not Compliant

8.3.2
In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually
loaded from the storage device.
When using Mobile DiskOnChip Plus as the system boot device, the CPU fetches the first
instructions from the Mobile DiskOnChip Plus Programmable Boot Block, which contains the IPL.
Since in most cases this block cannot hold the entire boot loader, the IPL runs minimum
initialization, after which the Secondary Program Loader (SPL) is copied to RAM from flash. The
remainder of the boot loader code then runs from RAM.
The IPL and SPL are located in a separate (binary) partition on Mobile DiskOnChip Plus, and can
be hardware protected if required.
For further information on software boot code implementation, refer to application note AP-DOC-
044, Writing an IPL for DiskOnChip Plus 16MByte Devices.
8.3.3
Platforms that host CPUs that wake up in burst mode should use Asynchronous Boot mode when
using Mobile DiskOnChip Plus as the system boot device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch
cycles continuously. An XScale CPU, for example, initiates a 16-bit read cycle, but after the first
word is read, it continues to hold CE# and OE# asserted while it increments the address and reads
additional data as a burst. A StrongARM CPU wakes up in 32-bit mode and issues double-word
instruction fetch cycles.
Since Mobile DiskOnChip Plus derives its internal clock signal from the CE#, OE# and WE#
inputs, it cannot distinguish between these burst cycles. To support this type of access, Mobile
DiskOnChip Plus needs to be set in Asynchronous Boot mode.
To set Mobile DiskOnChip Plus in Asynchronous Boot mode, set the byte RAM MODE SELECT
to 8FH. This can be done through the Mobile DiskOnChip Plus format utility or by customizing the
IPL code. For more information on the format utility, refer to the DiskOnChip Software Utilities
user manual or the TrueFFS Software Development Kit (SDK) developer guide. For further details
on customizing the IPL code, refer to application note AP-DOC-044, Writing an IPL for
DiskOnChip Plus 16MByte.
Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the Mobile
DiskOnChip Plus Programmable Boot Block. After reading from this block and completing boot,
Mobile DiskOnChip Plus returns to derive its internal clock signal from the CE#, OE# and WE#
inputs. Please refer to Section 10.4 for read timing specifications for Asynchronous Boot mode.
44
Non-PC Architectures
Using Mobile DiskOnChip Plus in Asynchronous Boot Mode
Data Sheet, Rev. 1.8
Mobile DiskOnChip Plus 16/32MByte
95-SR-000-10-8L