MD3331-D64-V3-X SanDisk, MD3331-D64-V3-X Datasheet - Page 48

• Manufacturer Part Number: MD3331-D64-V3-X
• Manufacturer: SanDisk
• Type: Flash Diskr

Specifications of MD3331-D64-V3-X

• Density: 64MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: FBGA
• Mounting: Surface Mount
• Pin Count: 69
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Not Compliant

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Mobile DiskOnChip Plus derives its internal clock signal from the CE#, OE# and WE# inputs.
Since access to Mobile DiskOnChip Plus’ registers is volatile, much like a FIFO or UART, ensure
that these signals have clean rising and falling edges, and are free from ringing that can be
interpreted as multiple edges. PC board traces for these three signals must either be kept short or
properly terminated to guarantee proper operation.
9.3.2
Mobile DiskOnChip Plus can also be configured to work with a multiplexed interface where data
and address line are multiplexed. In this configuration, AVD# input is driven by the host's AVD#
signal, and the D[15:0] pins, used for both address and data, are connected to the host AD[15:0]
bus. DiskOnChip address lines A[12:0] and BHE# should be connected to VSS. IF_CFG should be
connected to VCC.
Note: When used in a multiplexed interface, it is not possible to cascade Mobile DiskOnChip Plus
This mode is automatically entered when a falling edge is detected on AVD# input. This edge must
occur after RSTIN# is negated and before OE# and CE# are both asserted, i.e. the first read cycle
made to Mobile DiskOnChip Plus must observe the multiplex mode protocol.
Please refer to Section 2.3 for pinout and signal descriptions and to Section 10.4.3 for timing
specifications for a multiplexed interface.
9.4
9.4.1 Hardware Configuration
To configure the hardware, connect the IRQ# pin to the host interrupt input.
Note: A nominal 10 KΩ pull-up resistor must be connected to this pin.
9.4.2
Configuring the software to support the IRQ# interrupt is performed in two stages.
Stage 1
Configure the software so that upon system initialization, the following steps occur:
1.
48
Byte High Enable (BHE#) – This signal definition is compatible with 16 bit platforms that use
the BHE#/BLE# protocol. This signal is only relevant during the boot phase.
Hardware Lock (LOCK#) – This signal prevents the use of the write protect key to disable the
protection.
8/16 Bit Configuration (IF_CFG) – This signal is required for configuring the device for 8 or
16-bit access mode. When negated, the device is configured for 8-bit access mode. When
asserted, 16-bit access mode is operative.
The correct value is written to the Interrupt Control register to configure Mobile DiskOnChip
Plus for:
o
32MB.
Multiplexed Interface
Implementing the Interrupt Mechanism
Software Configuration
Interrupt source: Flash ready and/or data protection
Data Sheet, Rev. 1.8
Mobile DiskOnChip Plus 16/32MByte
95-SR-000-10-8L