FW82544EI Intel, FW82544EI Datasheet - Page 14

• Manufacturer Part Number: FW82544EI
• Manufacturer: Intel

Specifications of FW82544EI

• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

82544EI/82544GC SPECIFICATION UPDATE
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Transmit Delayed Interrupt Canceled but No Immediate Interrupt Generated
Message Signaled Interrupts Require Quad Word Data Alignment
Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers
I/O Read Cycles Can Cause Subsequent Incorrect Data Reads
The 82544EI/82544GC controller has a mechanism to cause delayed (TXDW) interrupts. If IDE is set in the
transmit descriptor, a timer value is loaded from the TIDV register. When the timer expires, an interrupt is
generated. If a later descriptor is processed with IDE=0, the controller correctly stops the countdown and clears
the counter. However, it does not generate an immediate interrupt as expected.
Software drivers that rely on a mixture of delayed and non-delayed transmit interrupts may not work
satisfactorily.
Use the delayed interrupt feature for all transmit descriptor interrupts, or for none of them. Intel drivers typically
use IDE=1 for all descriptors, but program diminishing timer values into TIDV when buffer resources are low.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controller.
Message signaled interrupts must be programmed such that the message data is written to addresses aligned
on quad word (8 byte) boundaries. The PCI specification only requires DWORD alignment.
If MSI writes are allowed to a DWORD aligned address, data corruption could occur.
Use care in programming the Message Capability Structure or do not use the MSI capability.
Intel resolved this erratum in the A1 stepping of the 82544EI/82544GC Gigabit Ethernet Controller.
Receive descriptors are typically written back to memory either upon receive interrupts or opportunistically in
between writing data buffers. When a received Ethernet packet exceeds the size of a single receive buffer,
corrupted receive descriptor writebacks may occur and the controller may hang. The conditions for this erratum
are specific:
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Corrupted descriptor writebacks may include writing back unconsumed descriptors, descriptor writebacks to
incorrect addresses, or writebacks missed altogether. In addition, the device may cease to access the PCI bus
or cease packet reception. If the device hangs, a full software or hardware reset is needed.
If the system uses buffers smaller than the maximum allowed packet size, take the following precautions:
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Intel resolved this erratum in A2 stepping of the 82544EI/82544GC Gigabit Ethernet Controller.
For any I/O read cycle with AD [2:0] = 000b, the 82544EI/82544GC controller initiates an internal register read
cycle. This behavior occurs even if the I/O cycle is not intended for the 82544EI/82544GC device. Subsequent
reads from 82544EI/82544GC controller register space (I/O or memory operations) may return erroneous data.
This problem is related to Erratum #1, “Erroneous Response to I/O Cycles”, which was corrected.
Systems may boot, but are prone to crash or blue screen later.
Place the 82544EI/82544GC controller on a subordinate PCI or PCI-X bus with no other I/O mapped devices. In
systems with multiple PCI buses, the subordinate bus is likely to be the bus with the highest speed and bus
width.
Intel resolved this erratum in A2 stepping of the 82544EI/82544GC Gigabit Ethernet Controller.
The controller is programmed to write back receive descriptors upon a receive interrupt, the interrupt has
The controller has a programmed descriptor writeback threshold (RXDCTL.WTHRESH), the number of
Configure the receive interrupt to occur immediately on end-of-packet by programming RIDV = 0.
Configure the descriptor writeback threshold WTHRESH to a value that will not result in a writeback in the
not yet been triggered, and
receive descriptors consumed thus far by the packet is equal to or greater than the threshold.
middle of a packet. Packets may be 1514 bytes or up to 16K bytes if long packets are enabled. It is
recommended that the RXDCTL.GRAN bit be set to 1 descriptor and WTHRESH set to the maximum
number of descriptor buffers the maximum size packet will consume.