FW82544EI Intel, FW82544EI Datasheet - Page 17

• Manufacturer Part Number: FW82544EI
• Manufacturer: Intel

Specifications of FW82544EI

• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Problem:
Workaround:
Status:
14. PCI-X FLASH Memory Write Problem with Specific Chipset
Implication:
15. Illegal Oversize Packets Overflow Receive FIFO
Problem:
Implication:
Workaround:
Status:
16. Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000
Problem:
Implication:
Workaround:
Status:
In certain PCI-X systems, utility programs cannot properly write FLASH memory connected to the Ethernet
controller.
Corrupted FLASH write cycles have been observed in a particular PCI-X based 8-way server based on the
Profusion chipset. The problem occurs when the PB64 PCI-X bridge attempts to write the FLASH using valid
64-bit PCI-X bus cycles. The 82544EI/82544GC controller correctly signals that it does not accept the 64-bit
cycle by deasserting ACK64. Then the system re-attempts the write operation with two 32-bit cycles. One of
those cycles is a "zero byte write" cycle that does not assert any C/BE# byte enable signals. The zero byte write
cycle confuses the FLASH memory controller in the 82544EI/82544GC device, resulting in a spurious bus cycle
to the FLASH memory. CS# and WE# are likely to be asserted improperly.
Several 8-way servers use the Profusion chipset and it is believed that all of them can encounter the problem.
Other PCI-X systems are not affected because they do not issue the 64-bit write cycle followed by 32-bit cycles
with a zero byte write. Problems have not been observed in standard PCI-based systems. LAN-on-motherboard
designs do not generally use FLASH memory connected to the 82544EI/82544GC controller.
Unmodified FLASH programming utilities will not work on certain PCI-X systems.
Use a FLASH programming utility with I/O FLASH addressing instead of memory-mapped FLASH addressing.
Intel has modified the FBOOT utility (v4.16) and the FUTIL (v4.16) utilities to use I/O FLASH addressing. The
GT utility already had an I/O addressing mode. Intel's PROSet LAN adapter utility program and the BROW utility
(v2.16) are currently being modified.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/GC Gigabit Ethernet Controller.
The controller should drop invalid Ethernet packets, but frames exceeding the maximum legal size can overflow
the receive FIFO, causing a lock up. This problem has only been reported in a test environment with an IXIA
packet generator.
The 82544EI/82544GC controller can receive jumbo frames up to 16K without difficulty. If the controller locks up
due to an oversize packet, a full software or hardware reset is needed.
Driver software should ensure that a minimum of 16K is allocated to the receive FIFO. Packets larger than this
size should not be present on the LAN.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controller.
If the controller calculates a transmit TCP checksum as 0x0000, it will automatically change the checksum to
0xFFFF.
Specifications call for 0xFFFF be substituted for 0x0000 for UDP packets to distinguish UDP packets that carry
no checksum. However, the modification does not apply to TCP packets.
If the receiving station is running MS-DOS and calculates a receive checksum of 0x0000, it will flag an error if
the checksum contained in the packet is 0xFFFF. Other operating systems treat 0x0000 and 0xFFFF as
equivalent in one’s complement math. UDP checksums are correct.
Intel modified the DOS Ethernet driver to check for a received checksum of 0xFFFF on a TCP/IP packet and
change it back to 0x0000 before passing the packet to the operating system.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controller.
82544EI/82544GC SPECIFICATION UPDATE
15