FW82544EI Intel, FW82544EI Datasheet - Page 24

• Manufacturer Part Number: FW82544EI
• Manufacturer: Intel

Specifications of FW82544EI

• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

82544EI/82544GC SPECIFICATION UPDATE
34. Transmit Descriptors May Be Written Back to Host, Even Without the RS Bit Set
Problem:
Implication
Workaround
Status:
35. Polarity Detection Error May Cause Inability to Transmit
Problem:
Implication
Workaround
Status:
22
:
:
:
:
If the RS bit is set on at least some transmit descriptors submitted to the device, it is possible that some other
transmit descriptors without the RS bit set will be incorrectly written back to host memory.
The unnecessary descriptor write-backs will not cause a functional issue, but they may result in a small amount
of unnecessary host bus bandwidth to be consumed.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controller.
The PHY component inside the 82544EI/GC contains logic to detect the polarity of the cable being used. In this
case, "polarity" refers to which wire of each pair is '+' and which is '-'. When the speed is forced to 10Mbps, and
the 82544EI/GC attempts to establish link under heavy traffic, the PHY may incorrectly interpret end-of-packet
symbols as inverted Normal Link Pulses. When this occurs, the PHY will establish link with the incorrect
polarity.
When the PHY detects the incorrect polarity, the MAC will see numerous errors of all kinds. It will not be able to
transmit nor receive properly.
This situation can be avoided in two ways:
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controller.
1.
2.
Disable the Polarity Reversal feature by setting bit 1 of the PHY Specific Control Register (16d) to 1b.
Avoid receiving packets until polarity is detected.
Drivers can implement option 2 by first, disabling the PHY's transmitter for 150ms, which will cause
the link partner to drop link. Then force the PHY to 10Mbps and re-enable the PHY's transmitter.
In terms of registers, the PHY’s transmitter can be powered down by writing:
It can be re-enabled by writing:
Write Register 0x1D = 0x0019
Write Register 0x1E = 0xFFFF
Write Register 0x1D = 0x0019
Write Register 0x1E = 0xFFF0
Write Register 0x1E = 0xFF00