FW82544EI Intel, FW82544EI Datasheet - Page 3

• Manufacturer Part Number: FW82544EI
• Manufacturer: Intel

Specifications of FW82544EI

• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CONTENTS
CONTENTS .....................................................................................................................................................1
PREFACE .......................................................................................................................................................4
NOMENCLATURE ..........................................................................................................................................4
COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE ............................................................5
GENERAL INFORMATION .............................................................................................................................5
SUMMARY TABLE OF CHANGES .................................................................................................................7
SPECIFICATION CHANGES......................................................................................................................... 10
ERRATA........................................................................................................................................................ 11
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82544EI/82544GC Component Marking Information .................................................................................5
Codes Used in Summary Tables...............................................................................................................7
TCP Segmentation (Large Send Offload)....................................................................................... 10
Erroneous Response to I/O Cycles ................................................................................................ 11
Bridge I/O Window Aperture May Lead to I/O Access Problems..................................................... 11
Device Does Not Always Check for PAR64 Errors ......................................................................... 11
Undersize Wakeup Packets Can Cause Wakeup........................................................................... 11
Transmit Delayed Interrupt Canceled but No Immediate Interrupt Generated................................. 12
Message Signaled Interrupts Require Quad Word Data Alignment ................................................ 12
Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers............................. 12
I/O Read Cycles Can Cause Subsequent Incorrect Data Reads .................................................... 12
Certain Registers Cannot Be Written with Particular Alignments in PCI-X Bus Operation............... 13
Multiple Buffers Needed for Jumbo Frames Larger than 8 Kilobytes in PCI-X Bus Operation......... 13
PCI-X Violation of FRAME# and GNT# Protocol ............................................................................ 13
EEPROM FLASH Disable Bit Must Not Be Set .............................................................................. 14
Improper Factory Test Pin Initialization .......................................................................................... 14
PCI-X FLASH Memory Write Problem with Specific Chipset .......................................................... 15
Illegal Oversize Packets Overflow Receive FIFO ........................................................................... 15
Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000 .......................................... 15
Odd Offset Register Writes in PCI-X Bus Operation....................................................................... 16
Link Failures with Short Cables...................................................................................................... 16
System Hang Due to Host Block Requests .................................................................................... 16
Transmit Descriptor Writeback Problems with Non-Zero WTHRESH.............................................. 17
Bus Initialization with Some Chipsets............................................................................................. 17
Packet Reception with APM Enabled before Driver Load ............................................................... 17
Intermittent Power-on State Due to Decoded High-Impedance Test Modes ................................... 18
32-Bit Split-Completion Dependency on subsequent REQ64# ....................................................... 18
Message Signaled Interrupt Feature May Corrupt Write Transactions............................................ 19
Link Establishment or Communication Problems
in Fiber Mode When Link Partner Does Not Fully Comply with the IEEE 802.3 Specification ......... 19
Wakeup Packet Memory (WUPM) cleared upon reset.................................................................... 19
82544EI/82544GC SPECIFICATION UPDATE
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