STA333BW STMicroelectronics, STA333BW Datasheet - Page 24

• Manufacturer Part Number: STA333BW
• Manufacturer: STMicroelectronics

Specifications of STA333BW

• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Audio Amplifier Function: Speaker
• Total Harmonic Distortion: 0.2@8Ohm@1W%
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 3.3/5/9/12/15/18V
• Power Supply Requirement: Quad
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 80dB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): 2.7/4.5V
• Dual Supply Voltage (max): 3.6/21.5V
• Operating Temp Range: -20C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Package Type: PowerSSO EP
• Lead Free Status / Rohs Status: Compliant

Register description
6.1.2
24/67
Thermal warning recovery bypass
Table 13.
This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled
the device automatically restores the normal gain and output limiting is no longer active. If it
is disabled the device keeps the output limit active until a reset is asserted or until TWRB set
to 0. This bit works in conjunction with TWAB
Thermal warning adjustment bypass
Table 14.
Bit TWAB enables automatic output limiting when a power stage thermal warning condition
persists for longer than 400ms. When the feature is active (TWAB = 0) the desired output
limiting, set through bit TWOCL (-3 dB by default) at address 0x37 in the RAM coefficients
bank, is applied. The way the limiting acts after the warning condition disappears is
controlled by bit TWRB.
Fault detect recovery bypass
Table 15.
The on-chip power block provides feedback to the digital controller which is used to indicate
a fault condition (either overcurrent or thermal). When fault is asserted, the power control
block attempts a recovery from the fault by asserting the 3-state output, holding it for period
of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant
register (FDRC registers 0x2B-0x2C), then toggling it back to normal condition. This
sequence is repeated as log as the fault indication exists. This feature is enabled by default
but can be bypassed by setting the FDRB control bit to 1. The fault condition is also
asserted by a low-state pulse of the normally high INT_LINE output pin.
Configuration register B (addr 0x01)
5
6
7
Bit
Bit
Bit
C2IM
D7
1
R/W
R/W
R/W
R/W
R/W
R/W
Thermal warning recovery bypass
Thermal warning adjustment bypass
Fault detect recovery bypass
C1IM
D6
0
1
1
0
RST
RST
RST
TWRB
TWAB
FDRB
DSCKE
D5
0
Doc ID 13773 Rev 3
Name
Name
Name
SAIFB
D4
0
0: thermal warning recovery enabled
1: thermal warning recovery disabled
0: thermal warning adjustment enabled
1: thermal warning adjustment disabled
0: fault detect recovery enabled
1: fault detect recovery disabled
SAI3
D3
0
SAI2
Description
Description
Description
D2
0
SAI1
D1
0
STA333BW
SAI0
D0
0