STA333BW STMicroelectronics, STA333BW Datasheet - Page 59
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STA333BW
Manufacturer Part Number
STA333BW
Description
Manufacturer
STMicroelectronics
Datasheet
1.STA333BW.pdf
(67 pages)
Specifications of STA333BW
Operational Class
Class-AB
Audio Amplifier Output Configuration
1-Channel Mono/2-Channel Stereo
Audio Amplifier Function
Speaker
Total Harmonic Distortion
0.2@8Ohm@1W%
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
3.3/5/9/12/15/18V
Power Supply Requirement
Quad
Rail/rail I/o Type
No
Power Supply Rejection Ratio
80dB
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
2.7/4.5V
Dual Supply Voltage (max)
3.6/21.5V
Operating Temp Range
-20C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
36
Package Type
PowerSSO EP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA333BW
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA333BW13TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA333BWJ13TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA333BWTR-9LF
Manufacturer:
ST
Quantity:
20 000
STA333BW
6.8
6.9
6.10
Note:
Variable max power correction registers (addr 0x27 - 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
Distortion compensation registers (addr 0x29 - 0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
Fault detect recovery constant registers (addr 0x2B - 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the
TRISTATE output is immediately asserted low and held low for the time period specified by
this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x000C gives approximately 0.1 ms.
0x0000 is a reserved value for these registers.
MPCC15
FDRC15
MPCC7
DCC15
FDRC7
DCC7
D7
D7
D7
D7
D7
D7
0
1
1
0
0
0
MPCC14
FDRC14
MPCC6
DCC14
FDRC6
DCC6
D6
D6
D6
D6
D6
D6
0
1
1
0
0
0
MPCC13
FDRC13
MPCC5
DCC13
FDRC5
DCC5
D5
D5
D5
D5
D5
D5
0
0
1
1
0
0
Doc ID 13773 Rev 3
MPCC12
FDRC12
MPCC4
DCC12
FDRC4
DCC4
D4
D4
D4
D4
D4
D4
1
0
1
1
0
0
MPCC11
FDRC11
MPCC3
DCC11
FDRC3
DCC3
D3
D3
D3
D3
D3
D3
1
0
0
0
0
1
MPCC10
FDRC10
MPCC2
DCC10
FDRC2
DCC2
D2
D2
D2
D2
D2
D2
0
0
0
0
0
1
Register description
MPCC9
MPCC1
FDRC9
FDRC1
DCC9
DCC1
D1
D1
D1
D1
D1
D1
1
0
1
1
0
0
MPCC8
MPCC0
FDRC8
FDRC0
DCC8
DCC0
D0
D0
D0
D0
D0
D0
0
0
1
1
0
0
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