TDA5250XT Infineon Technologies, TDA5250XT Datasheet

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heet, Versio n 1.7, 2 007-02-26 TDA5250 ...

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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

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heet, Versio n 1.7, 2 007-02-26 TDA5250 ...

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... Ordering Code 5, 10 correction of the Package Name 79 indication of the ESD-integrity values For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ® ® ® ABM ...

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ASK/FSK 868MHz Wireless Transceiver TDA5250 D2 Product Info General Description The low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 868-870MHz band. The IC offers a very high level of integration ...

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Table of Contents 1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Product Description 1.1 Overview The low power consumption single chip FSK/ASK Transceiver for the frequency band 868- 870 MHz. The IC combines a very high level of integration and minimum external part count. The device contains ...

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Application Low Bitrate Communication Systems Keyless Entry Systems Remote Control Systems Alarm Systems Telemetry Systems Electronic Metering Home Automation Systems 1.4 Package Outlines Figure 1-1 PG-TSSOP-38 package outlines Data Sheet Product Description 10 TDA5250 D2 Version 1.7 PG-TSSOP-38.EPS 2007-02-26 ...

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Functional Description 2.1 Pin Configuration VCC BUSMODE LF ____ ASKFSK __ RxTx LNI LNIx GND1 GNDPA PA VCC1 PDN PDP SLC VDD BUSDATA BUSCLK VSS XOUT Figure 2-1 Pin Configuration Data Sheet TDA5250 ...

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Pin Definitions and Functions Table 2-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic 1 VCC 2 BUSMODE ASKFSK Data Sheet 350 2 200 350 4 12 TDA5250 D2 Version 1.7 ...

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RXTX 5 6 LNI 6 7 VCC 8 BUSMODE 8 9 GNDPA VCC1 Data Sheet 350 1.1V 7 180 180 PWDN PWDN see Pin see Pin 8 10 ...

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PDN 12 13 PDP 13 14 SLC 14 15 VDD 16 BUSDATA 16 17 BUSCLK 18 VSS Data Sheet 50k 50k PWDN 350 3k 50k 50k 350 3k PWDN 50k 50k 1.2uA 350 50k 50k 50k 50k 1.2uA see ...

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XOUT Vcc 20 XSWF 21 XIN 22 XSWA 23 XGND 24 EN Data Sheet 4k Vcc-860mV 150µA 125fF ..... 4pF 250fF ..... 8pF see Pin see Pin 22 350 24 15 TDA5250 D2 Version 1.7 ...

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RESET 25 26 CLKDIV 26 27 PWDDD 27 28 DATA 28 29 RSSI 29 Data Sheet Reset of the entire system (to default values), active low 110k 350 10p Clock output 350 Power Down input (active high), data detect ...

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GND 31 CQ2x 31 32 CQ2 33 CI2x 34 CI2 35 CQ1x 36 CQ1 37 CI1x 38 CI1 Data Sheet see Pin 8 Analog ground Pin for external Capacitor Q-channel, stage 2 Stage1:Vcc-630mV Stage2: Vcc-560mV II Q-channel, stage 2 ...

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Functional Block Diagram BUSMODE __ EN BUSCLK BUSDATA SLC CQ2x 31 32 CQ2 33 CI2x 34 CI2 35 CQ1x 36 CQ1 37 CI1x 38 CI1 (digital) (analog) (LNA/PA) Figure 2-2 Main Block Diagram Data Sheet Functional Description TDA5250D1_blockdiagram_aktuell.wmf 18 ...

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Functional Block Description 2.4.1 Power Amplifier (PA) The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V ...

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PLL Synthesizer The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop filter ...

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FSK Demodulator The output differential signals of the I/Q limiters are fed to a quadrature correlator circuit that is used to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation is ±300kHz as ...

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ASK / FSK INTERNAL BUS Figure 2-5 Data Filter architecture 2.4.10 Data Slicer The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is generated by a RC-network (LPF use of one or ...

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Table 2-5 PwdDD Pin Operating States PwdDD VDD Ground/VSS 2.4.14 Timing and Data Control Unit The timing and data control unit contains a wake-up logic unit interface, a “data valid” detection unit and a set of configuration registers ...

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The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine ...

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Data Transition: Data transition on the pin BusData can only occur when BusCLK is LOW. BusData transitions while BusCLK is HIGH will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a HIGH ...

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Table 2 Bus Write Mode 8 Bit MSB CHIP ADDRESS LSB (WRITE) STA Table 2 Bus Write Mode 16 Bit MSB CHIP ADDRESS (WRITE) LSB STA ...

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Bus Data Format 3-wire Bus Mode Table 2-11 3-wire Bus Write Mode MSB SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH,0FH Table 2-12 3-wire Bus Read Mode MSB SUB ADDRESS (READ) 80H, 81H ...

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Subaddress Organization Table 2-13 Sub Addresses of Data Registers Write MSB ...

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Subaddress Organization Table 2-16 Sub Addresses of Data Registers Write MSB ...

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Table 2-19 Sub Address 01H: FSK Bit Function Value Description D15 D14 D13 FSK+5 8pF D12 FSK+4 4pF D11 FSK+3 2pF shift: +FSK or D10 FSK+2 1pF D9 FSK+1 500fF D8 FSK+0 250fF FSK-5 4pF D4 FSK-4 ...

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Table 2-25 Sub Address 08H: RSSI_TH3 Bit Function Description D7 not used D6 SELECT 0= VCC, 1= RSSI D5 TH3_5 D4 TH3_4 D3 TH3_3 D2 TH3_2 D1 TH3_1 D0 TH3_0 Table 2-27 Bit Function ...

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Wakeup Logic SELF POLLING Figure 2-9 Wakeup Logic States Table 2-31 MODE settings: CONFIG register MODE_1 SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx, AskFsk, ...

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Note: The time delay between start of ON time and the 15µs LOW impulse is 2.6ms + 3 period of data rate. If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is applied at PwdDD ...

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Figure 2-13 Data Valid Circuit D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28. RxTxint and TX_ON are internally generated signals and power down mode Data pin (Pin 28) is tied to ...

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With default settings the clock generating units are disabled during PD, therefore no clock is available at the clock output pin possible to offer a clock signal at the clock output pin every time (also during PD) if ...

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This means that the device needs t When activating TX it requires t For timing information refer to Table 4.3. For test purposes a TESTMODE is provided by the Sequencer as well. In this mode the BLOCK_PD register be set ...

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Table 2-32 CLK_DIV Output Selection Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2- 16, t CLKSU ). Table 2-33 CLK_DIV ...

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To prevent wrong interpretation of the ADC information (read from Register 81H: ADC) you can use the ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement. Note: As shown in Section ...

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Application 3.1 LNA and PA Matching 3.1.1 RX/TX Switch RF I/O 50 Ohm SMA-connector Figure 3-1 RX/TX Switch The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMA- connector. Two pin-diodes are used as switching ...

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RF I/O 50 Ohm SMA-connector open or VCC Figure 3-2 RX-Mode The RF-signal is able to run from the RF-input-SMA-connector to the LNA-input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the matching circuit due to ...

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Measured Magnitude of S11 of evalboard: Figure 3-3 S11 measured Above you can see the measured S11 of the evalboard. The –3dB-points are at 810MHz and 930MHz. So the 3dB-bandwidth is: = − 930 MHz U ...

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This will cause problems in a tuning-free mass production of the application. A good CAE-tool will help to see the effects of component tolerances on the input matching more accurate by tweaking each ...

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RF I/O 50 Ohm SMA-connector grounded (with jumper or RX/TX-pin of IC) Figure 3-4 TX_Mode R1 does not influence the matching because of its very high resistance. Due to the large capacitance of C1, C6 and C5 the circuit can ...

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Power-Amplifier The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of θ<<π. A frequency selective network at the amplifier ...

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The diagram of Figure 3-7 has been measured directly at the PA-output at V the matching circuit of about 2dB will decrease the output power. As shown in the diagram, 240 Ohm ...

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Figure 3-8 Power output and collector current vs. frequency C4, L2 and C3||C2 are the main matching components which are used to transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at the PA-output (240Ohm@3V). L1 can ...

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Figure 3-9 Sparam_measured_200M Above you can see the measurement of the evalboard with a span of 200MHz. The evalboard has been optimized for 3V. The load is about 240+j0 at 868.3MHz. A tuning-free realization requires a careful design of the ...

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Figure 3-10 Transmit Spectrum 13.2GHz Figure 3-11 Transmit Spectrum 300MHz Regarding CEPT ERC recommendation 70-03 and ETSI regulation EN 300220 both of the following figures show full compliance in case of ASK and FSK modulation spectrum. Data signal is a ...

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Figure 3-12 ASK Transmit Spectrum 25kBaud, Manch, PRBS9, 9dBm, 3V Figure 3-13 FSK Transmit Spectrum 40kBaud, Manch, PRBS9, 9dBm, 3V Data Sheet ASK_25kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf FSK_40kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf 49 TDA5250 D2 Version 1.7 Application 2007-02-26 ...

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Crystal Oscillator The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. Here also the load capacitance of the crystal which the crystal wants to ...

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S δ − δ δ Choosing large as possible results in a small pulling ...

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Figure 3-15 Crystal Oscillator 1 = ↔ ω − OSC ω OSC With the aid of this formula it becomes obvious that the higher the serial ...

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With C and C the necessary Alternatively, an external AC coupled (10nF in series to 1k The drive level should be approximately 100mVpp. 3.2.1 Synthesizer Frequency setting Generating ASK and FSK modulation 3 setable frequencies ...

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COSC HI RF DEV e. (868,3E6 + 50E3 18.08438MHz COSC (868,3E6 - 50E3 18.08229MHz COSC LOW with a frequency deviation of ...

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Figure 3-17 FSK modulation In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus the frequency may be calculated 48, COSC RF e. 868,3E6 ...

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Parasitics For the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches ( have to be taken into account Figure 3-19 ...

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Note: Please keep in mind also to include the Pad parasitics of the circuit board. 3.2.4 Calculation of the external capacitors 1. Determination of necessary crystal frequency using formula [4-19]. e. FSK- COSC LOW 2. Determine corresponding ...

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In the bipolar mode the FSK-switch can be controlled by a ramp function. This ramp function is set by the bits D1 and D2 of the XTAL_CONFIG register (subadress 0EH). With these modes of the FSK-switch the bandwidth of the ...

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D5 FSK-5 D4 FSK-4 D3 FSK-3 D2 FSK-2 D1 FSK-1 D0 FSK-0 Default values In case of using the evaluation board, the crystal with its typical parameters (fp=18.08958MHz, C =8fF, C =2,08pF, C =12pF) and external capacitors with Cv1=4.7pF, Cv2=1.8pF, ...

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Concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature stability, tolerance have to be considered. In addition to the chip tolerances also the crystal and external component tolerances have to be ...

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Figure 3-20 I/Q Filter Characteristics -f 3dB IQ Filter Figure 3-21 IQ Filter and ...

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Table 3-10 3dB cutoff frequencies Data Filter ...

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The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch. This time is hard wired and independent from external capacitors pins 31 to 38. The maximum value for this capacitors is 47nF. RSSI accuracy settling ...

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Figure 3-24 Typ. RSSI Level (Eval Board) @3V 3.6 Data Slicer - Slicing Level The data slicer is an analog-to-digital converter necessary to ...

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Figure 3-25 Slicer Level using RC Integrator 3.6.2 Peak Detectors Table 3-13 Sub Address 00H: CONFIG Bit Function D15 SLICER The TDA5250 has two peak detectors built in, one for positive peaks in the data stream and the other for ...

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Figure 3-26 Slicer Level using Peak Detector For applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak detectors. The threshold value is generated by an internal voltage divider. The release time ...

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Component calculation: (rule of thumb) ⋅ ≥ Ω 100k T – longest period of no signal change (LOW signal) L1 ⋅ ≥ Ω 100k T – longest period of no ...

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Figure 3-29 Peak detector - power down mode Signal Vcc Neg. Peak Detector (pin12) Pos. Peak Detector (pin13) 0 Power ON Figure 3-30 Power down mode 3.7 Data Valid Detection In order to detect valid data two criteria must be ...

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Timing for data detection looks like the following. Two settings are possible: „Continuous“ and „Single Shot“, which can be set by D5 and D6 in register 00H. Sequenzer enables data detection Counter Reset Compare with single TH and latch result ...

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Frequency Window for Data Rate Detection The high time of data is used to measure the frequency of the data signal. For Manchester coding either the data frequency or half of the data frequency have to be detected corresponding ...

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This yields the following results: which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and COUNT_TH2 registers (subaddresses 06H and 07H), respectively. Default values (window counter inactive): TH1= 000000000000 b TH2= 000000000001 b Note: The ...

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Default values: ON= 65215 = 1111111011000000 OFF= 62335 = 1111001110000000 t ~10ms @ f = 32kHz ~100ms @ f = 32kHz OFF RC 3.9 Example for Self Polling Mode The settings for Self Polling Mode depend very ...

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This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA mean current consumption in Self Polling Mode. The resulting worst case timing is shown in the following figure: Case A: Case B: Case C: ...

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WinQSIM via a GPIB interface. The AMIQ generator has a pseudo random binary sequence (PRBS) generator and a bit error test set built in. The resulting I/Q signals are applied to the SMIQ to generate a ASK (OOK) ...

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The best sensitivity performance can be achieved using a data filter bandwidth of 1.25 times the maximum occuring data frequency. The IQ filter setting is depending on the modulation type. ASK needs an IQ filter of 50kHz, 50kHz deviation at ...

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BER performance depending on Supply Voltage Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph. Figure 3-38 BER supply voltage Please notice the tiny ...

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Figure 3-39 Datarates and Sensitivity 3.10.5 Sensitivity at Frequency Offset Applying the test setup in Figure 3-36 even a wide offset in the received frequency spectrum results only in a slight decrease of receiving sensitivity offset of 100kHz ...

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Default Setup Default setup is hard wired on chip and effective after a reset or return of power supply. Table 3-14 Default Setup Parameter IQ-Filter Bandwidth Data Filter Bandwidth Limiter lower fg Slicing Level Generation Nom. Frequency Capacity intern ...

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Reference 4.1 Electrical Data 4.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 4-1 Absolute Maximum Ratings # Parameter ...

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AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Table 4-3 AC/DC Characteristics with T # Parameter RECEIVER Characteristics 1 Supply current ...

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Table 4-3 AC/DC Characteristics with T # Parameter TRANSMITTER Characteristics 1 Supply current TX, FSK 2 Supply current TX, FSK 3 Supply current TX, FSK 4 Output power 5 Output power 6 Output power 7 Supply current TX, FSK 8 ...

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Table 4-4 AC/DC Characteristics with T # Parameter GENERAL Characteristics 1 Power down current timer mode (standby) 2 Power down current timer mode (standby) 3 Power down current with XTAL ON 4 Power down current with XTAL ON 5 32kHz ...

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Digital Characteristics Bus Timing BusMode = LOW t BUF BusData BusCLK H D. HIG H EN pulsed or t mandatory low SU. ENAS DA t SU. ENAS DA ...

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Table 4-5 Digital Characteristics with T # Parameter 1 Data rate TX ASK 2 Data rate TX ASK 3 Data rate TX FSK 4 Data rate RX ASK 5 Data rate RX FSK 6 Digital Inputs High-level Input Voltage Low-level ...

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Parameter 14 LOW period of BusCLK clock 15 HIGH period of BusCLK clock 16 Setup time for a repeated START condition 17 Data hold time 18 Data setup time 19 Rise, fall time of both BusData and BusCLK signals ...

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Test Circuit The device performance parameters marked with evaluation board (IFX board). Figure 4-3 Schematic of the Evaluation Board Data Sheet in Section 4.1.3 were measured on an Infineon 86 TDA5250 D2 Version 1.7 Reference TDA5250_v42.schematic.pdf 2007-02-26 ...

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Test Board Layout Gerberfiles for this Testboard are available on request. Figure 4-4 Layout of the Evaluation Board Note 1: The LNA and PA matching network was designed for minimum required space and maximum performance and thus via holes ...

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Bill of Materials Table 4-6 Bill of Materials Reference R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 ...

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Table 4-6 Bill of Materials Reference C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 IC1 IC2 IC3 D1 Data Sheet Value ...

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List of Tables Table 2-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 3-10 3dB cutoff frequencies Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-11 Limiter Bandwidth ...

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List of Figures Figure 1-1 PG-TSSOP-38 package outlines page Figure 2-1 Pin Configuration. ...

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List of Figures Figure 3-25 Slicer Level using RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Figure ...

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Index A Absolute Maximum Ratings 80 AC/DC Characteristics 10, 39 Application E 79 Electrical Data F 9 Features Functional Block Description 18 Functional Block Diagram 11 Functional Description Data Sheet O 79 Operating Range Overview P Package Outlines Pin Configuration ...