SC28L92A1B NXP Semiconductors, SC28L92A1B Datasheet - Page 46

• Manufacturer Part Number: SC28L92A1B
• Description: UART Interface IC UART DUAL W/FIFO
• Manufacturer: NXP Semiconductors
• Type: Dual UARTr

Specifications of SC28L92A1B

• Number Of Channels: 2
• Data Rate: 230.4 Kbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PQFP-44
• Description/function: Single-chip CMOS-LSI communications device
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / Rohs Status: Details
• Other names: SC28L92A1B,557

NXP Semiconductors
SC28L92_7
Product data sheet
Table 58.
Bit
6
5
4
3
2
1
0
Symbol
-
RxRDYB
TxRDYB
-
-
RxRDYA
TxRDYA
ISR - Interrupt status register (address 0x5) bit description
Description
Channel B change in break.
This bit, when set, indicates that the channel B receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel B reset break change interrupt command.
RxB interrupt.
This bit indicates that the channel B receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
TxB interrupt.
This bit indicates that the channel B transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
Counter ready.
In the counter mode, this bit is set when the counter reaches terminal count and
is reset when the counter is stopped by a stop counter command.
In the timer mode, this bit is set once each cycle of the generated square wave
(every other time that the counter/timer reaches zero count). The bit is reset by a
stop counter command. The command, however, does not stop the
counter/timer.
Channel A change in break.
This bit, when set, indicates that the channel A receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel A reset break change interrupt command.
RxA interrupt.
This bit indicates that the channel A receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
TxA interrupt.
This bit indicates that the channel A transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
…continued
SC28L92
© NXP B.V. 2007. All rights reserved.
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