PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 123

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

8.0 Legacy Functional Blocks
8.2 PARALLEL PORT
8.2.1
The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP),
Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).
8.2.2
The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second
level offset registers are available only when base address is 8-byte aligned.
General Description
Parallel Port Register Map
First Level
Offset
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
Table 34. Parallel Port Register Map for Second Level Offset
Mnemonic
Table 33. Parallel Port Register Map for First Level Offset
CNFGA
CNFGB
DATAR
AFIFO
DATA0
DATA1
DATA2
DATA3
CFIFO
DFIFO
ADDR
TFIFO
DSR
DCR
ECR
EDR
EAR
EIR
Second Level
PP Data
ECP Address FIFO
Status
Control
EPP Address
EPP Data Port 0
EPP Data Port 1
EPP Data Port 2
EPP Data Port 3
PP Data FIFO
ECP Data FIFO
Test FIFO
Configuration A
Configuration B
Extended Control
Extended Index
Extended Data
Extended Auxiliary Status
(Continued)
Offset
00h
02h
04h
05h
Register Name
Register Name
123
PP Confg0
Control0
Control2
Control4
Type
R/W
R/W
R/W
R/W
Modes (ECR Bits)
All Modes
All Modes
All Modes
All Modes
All Modes
All Modes
7 6 5
0 0 0
0 0 1
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0 1 0
0 1 1
1 1 0
1 1 1
1 1 1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
W
W
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