A25L040-F AMIC, A25L040-F Datasheet
A25L040-F
Specifications of A25L040-F
Related parts for A25L040-F
A25L040-F Summary of contents
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... Add packing description in Part Numbering Scheme 1.2 ata Retention and Endurance value from Max. P28: Change D to Min. (October, 2010, Version 1.2) A25L040 Series 4Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Issue Date April 10, 2009 May 3, 2010 October 20, 2010 AMIC Technology Corp ...
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... Single Supply Voltage SPI Bus Compatible Serial Interface 100MHz Clock Rate (maximum) GENERAL DESCRIPTION The A25L040 are 4M bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction ...
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... Read Dual Input-Output instruction is executed. (October, 2010, Version 1.2) High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Byte (Page Size) X Decoder A25L040 Series Status Register 7FFFFh (4M) Size of the memory area 000FFh Logic Symbol V CC DIO C S A25L040 ...
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... The main purpose of this input signal is Write Protect ( W to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register). AMIC Technology Corp. 3 A25L040 Series required ) signal is used to pause with the device without S ) driven Low ...
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... C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DO 4 A25L040 Series C DO DIO C DO SPI Memory SPI Memory Device Device S W HOLD S MSB AMIC Technology Corp. DIO W HOLD ...
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... Status Register (SRWD, BP2, BP1, BP0) become read-only bits. Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L040 boasts the following data protection mechanisms Power-On Reset and an internal timer (t W ...
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... To restart communication with the device necessary to drive Hold ( Chip Select ( back to the Hold condition. Hold Condition (standard use) 6 A25L040 Series Memory Content Unprotected Area 1 All blocks Lower seven-eighths (7 blocks Lower three-quarters (6 blocks Lower half (4 blocks None ...
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... A25L040 MEMORY ORGANIZATION The memory is organized as: 524,288 bytes (8 bits each) 8 64-Kbytes blocks 128 4-Kbytes sectors 2048 pages (256 bytes each). Table 2. Memory Organization A25L040 Address Table Block Sector 127 7 112 111 (October, 2010, Version 1.2) Each page can be individually programmed (bits are programmed from ...
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... A25L040 Series One-byte Address Dummy Bytes Bytes 06h 0 04h 0 05h 0 01h 0 03h 3 0Bh 3 ...
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... Write Disable (WRDI) instruction completion ﹣ Write Status Register (WRSR) instruction completion ﹣ Page Program (PP) instruction completion ﹣ Sector Erase (SE) instruction completion ﹣ Bulk Erase (BE) instruction completion Instruction DIO High Impedance DO 9 A25L040 Series S ) Low, sending the instruction code, and then S ) High AMIC Technology Corp. ...
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... Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB 10 A25L040 Series W ) signal allow the device to be put in the Status Register Out MSB AMIC Technology Corp signal. ...
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... Register Write Disable (SRWD) bit and Write Protect ( signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered initiated. While the Instruction 7 High Impedance MSB 11 A25L040 Series Status Register AMIC Technology Corp ...
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... Write Protect ( If Write Protect ( Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. 12 A25L040 Series Memory Content 1 Protected Area Unprotected Area Ready to accept Page ...
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... C Instruction DIO High Impedance DO Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) therefore, be read with a single Read Data Bytes (READ Low. instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... C Dummy Byte DIO DO Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) Speed (FAST_READ) instruction. When the highest address S ) Low. is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) ...
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... DIO DO Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device’s internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “ ...
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... The Fast Read Dual Input-Output (BBh) instruction is similar to the Fast_Read (0Bh) instruction except the data is input and output on two pins, DO and DIO, instead of just DO. This allows data to be transferred from the A25L040 at twice the rate of standard SPI devices. Similar to the Fast Read instruction, the Fast Read Dual ...
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... Data Byte 2 DIO MSB Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page ...
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... Figure 13. Sector Erase (SE) Instruction Sequence DIO Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) instruction is not executed. As soon as Chip Select ( driven High, the self-timed Sector Erase cycle (whose duration is t progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit ...
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... Block Erase Figure 14. Block Erase (BE) Instruction Sequence S C DIO Note: Address bits A23 to A19 are Don’t Care, for A25L040. (October, 2010, Version 1.2) instruction is not executed. As soon as Chip Select ( driven High, the self-timed Block Erase cycle (whose duration is t ...
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... The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE) instruction is ignored if one, or more, blocks are protected Instruction Note: Address bits A23 to A19 are Don’t Care, for A25L040. 20 A25L040 Series driven High AMIC Technology Corp. ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Instruction Stand-by Mode 21 A25L040 Series S ) Low, followed by the instruction code must be driven Low S ) must be driven High after the eighth bit of the ...
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... JEDEC, and has the value 37h. The device identification is assigned by the device manufacturer, and indicates the memory in the first bytes (30h), and the memory capacity of the device in the second byte (13h for A25L040). Any Read Identification (RDID) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress ...
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... Instruction 2 Dummy Bytes MSB ADD ( Manufacturer MSB 23 A25L040 Series S ) High at any time during driven High, the device is put in the Device Identification 12h (A25L040 Device MSB AMIC Technology Corp. MSB ...
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... C Instruction DIO High Impedance DO Note: The value of the 8-bit Electronic Signature, for the A25L040 is 12h. (October, 2010, Version 1.2) edge of Serial Clock (C). Then, the 8-bit Electronic Signature, and Read stored in the memory, is shifted out on Serial Data Output (DO), each bit being shifted out during the falling edge of Serial Clock (C) ...
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... Stand-by Power mode is delayed by t and Chip Select ( as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 25 A25L040 Series RES1 Stand-by Mode S ) must remain High for at least t AMIC Technology Corp. ...
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... Power-down occurs (min while a Write, Program or Erase cycle is in progress, some data corruption can result A25L040 Series t after V passed the VWI threshold PUW CC after V passed the V (min) level VSL ...
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... INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (October, 2010, Version 1.2) Parameter 27 A25L040 Series Min. Max. Unit 2.7 V ...
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... Designers should check that the operating conditions in their circuit match the measurement conditions when relying on performed under the the quoted parameters. Parameter Condition Test Condition OUT =25 ° C and a frequency of 33 MHz A25L040 Series Min. Max. 2.7 3.6 –40 85 Min. Max. 100,000 20 Min. Max AMIC Technology Corp. Unit V ° ...
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... Page Program Cycle Time PP t Sector Erase Cycle Time SE t Block Erase Cycle Time BE t Chip Erase Cycle Time of A25L040 CE Note ° C Table 14. AC Measurement Conditions Symbol C Load Capacitance L Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: Output Hi-Z is defined as the point where data out is no longer driven ...
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... Figure 22. AC Measurement I/O Waveform 0.8V 0.2V (October, 2010, Version 1.2) Input Levels A25L040 Series Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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... Page Program Cycle Time pp t Sector Erase Cycle Time SE t Block Erase Cycle Time BE t Chip Erase Cycle Time of A25L040 CE Note must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. ...
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... Figure 23. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (October, 2010, Version 1.2) tSLCH tCHDX MSB IN High Impedance High Impedance 32 A25L040 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Hold Timing Figure 25 DIO DO HOLD Figure 26. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (October, 2010, Version 1.2) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 33 A25L040 Series tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...
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... Part Numbering Scheme A25 X XXX * Optional (October, 2010, Version 1. A25L040 Series Packing Blank: for DIP8 G: for SOP8 In Tube Q: for Tape & Reel Package Material Blank: normal F: PB free Temperature* Blank = 0°C ~ +70° -40°C ~ +85°C Package Type M = 209 mil SOP 150 mil SOP 8 ...
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... Ordering Information Part No. Speed (MHz) A25L040-F A25L040O-F A25L040O-UF 100 A25L040M-F A25L040M- for industrial operating temperature range: -40°C ~ +85°C Blank is for commercial operating temperature range: 0 ° +70 ° C (October, 2010, Version 1.2) Active Read Program/Erase Current Current Max. (mA) Max. (mA A25L040 Series Standby Current Package Max. (μ ...
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... L 0.125 - - E 0.345 - 0.385 A S 0.016 0.021 0.026 do not include mold flash or protrusions. 1 does not include dambar protrusion A25L040 Series Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 ...
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... Dimensions in mm Symbol A 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6. 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). 4. Coplanarity: Max. 0.1mm 37 A25L040 Series L AMIC Technology Corp. unit: mm ...
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... E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads 38 A25L040 Series C θ L Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38 0.80 8° AMIC Technology Corp. unit: mm ...