A25L040-F AMIC, A25L040-F Datasheet - Page 10
![58T1307](/photos/40/61/406111/ge8dip-40_sml.jpg)
A25L040-F
Manufacturer Part Number
A25L040-F
Description
58T1307
Manufacturer
AMIC
Datasheet
1.A25L040-F.pdf
(39 pages)
Specifications of A25L040-F
Memory Type
Flash
Memory Size
4Mbit
Memory Configuration
4M X 1
Interface Type
Serial, SPI
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
DIP
No. Of Pins
8
Rohs Compliant
Yes
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
Figure 4. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5.) resets the
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip
Select (
Chip The Write Enable Latch (WEL) bit is reset under the
following conditions:
Figure 5. Write Disable (WRDI) Instruction Sequence
(October, 2010, Version 1.2)
S
) Low, sending the instruction code, and then driving
DIO
DIO
DO
DO
C
S
C
S
High Impedance
0 1
High Impedance
0 1
2 3
2 3
Instruction
Instruction
9
The Write Enable (WREN) instruction is entered by driving
Chip Select (
driving Chip Select (
﹣
﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Bulk Erase (BE) instruction completion
4 5
4 5
Power-up
6 7
6 7
S
) Low, sending the instruction code, and then
S
) High.
AMIC Technology Corp.
A25L040 Series