XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 11

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

2.5
When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and
tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.
2.5.1
2.5.2
Freescale Semiconductor
Signal Name
Signal Name
Signal Name
PINIT/NMI
D0–D23
PCAP
A0–A17
External Memory Expansion Port (Port A)
External Address Bus
External Data Bus
Type
Input
Input
Input/Output
Output
Type
Type
State during Reset
Input
Input
State during Reset
State during Reset
Table 2-4 Clock and PLL Signals (continued)
Table 2-5 External Address Bus Signals
Tri-Stated
Tri-Stated
Table 2-6 External Data Bus Signals
DSP56362 Technical Data, Rev. 4
PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL
filter. Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP may be tied to V
PLL Initial/Non maskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET deassertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input
is a negative-edge-triggered non maskable interrupt (NMI) request internally
synchronized to CLKOUT.
PINIT/NMI cannot tolerate 5 V.
Data Bus—When the DSP is the bus master, D0–D23 are active-high,
bidirectional input/outputs that provide the bidirectional data bus for
external program and data memory accesses. Otherwise, D0–D23 are
tri-stated.
Address Bus—When the DSP is the bus master, A0–A17 are
active-high outputs that specify the address for external program and
data memory accesses. Otherwise, the signals are tri-stated. To
minimize power dissipation, A0–A17 do not change state when
external memory spaces are not being accessed.
Signal Description
Signal Description
Signal Description
External Memory Expansion Port (Port A)
CC
, GND, or left floating.
CCP
2-5
.