XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 26

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

JTAG/OnCE Interface
2.12
2-20
Signal
Name
TRST
TDO
TMS
TCK
TDI
DE
JTAG/OnCE Interface
Input/Output
Output
Type
Input
Input
Input
Input
State During Reset
Tri-Stated
Input
Input
Input
Input
Input
Table 2-14 JTAG/OnCE™ Interface
DSP56362 Technical Data, Rev. 4
Test Clock—TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
This input is 5 V tolerant.
Test Data Input—TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
Test Data Output—TDO is a test data serial output signal used for test
instructions and data. TDO can be tri-stated and is actively driven in the
shift-IR and shift-DR controller states. TDO changes on the falling edge of
TCK.
Test Mode Select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK and
has an internal pull-up resistor.
This input is 5 V tolerant.
Test Reset—TRST is an active-low Schmitt-trigger input signal used to
asynchronously initialize the test controller. TRST has an internal pull-up
resistor.
The use of TRST is not recommended for new designs. It is recommended
to leave TRST disconnected.
This input is 5 V tolerant.
Debug Event—DE is an open-drain, bidirectional, active-low signal
providing, as an input, a means of entering the debug mode of operation
from an external command controller, and, as an output, a means of
acknowledging that the chip has entered the debug mode. This signal, when
asserted as an input, causes the DSP56300 core to finish the current
instruction being executed, save the instruction pipeline information, enter
the debug mode, and wait for commands to be entered from the debug serial
input line. This signal is asserted as an output for three clock cycles when
the chip enters the debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE has an internal pull-up resistor.
This is not a standard part of the JTAG TAP controller. The signal connects
directly to the OnCE module to initiate debug mode directly or to provide a
direct external indication that the chip has entered the debug mode. All other
interface with the OnCE module must occur through the JTAG port.
The use of DE is not recommended for new designs. It is recommended to
leave DE disconnected.
This input is not 5 V tolerant.
Signal Description
Freescale Semiconductor