LH28F800BJHE-PBTLT9 Sharp Microelectronics, LH28F800BJHE-PBTLT9 Datasheet - Page 21

• Manufacturer Part Number: LH28F800BJHE-PBTLT9
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8 90ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJHE-PBTLT9

• Package: 48TSOP
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT
SR.3 = V
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase, Full Chip Erase or Clear Block
0 = Successful Block Erase, Full Chip Erase or Clear
1 = Error in Word/Byte Write or Set Block/Permanent
0 = Successful Word/Byte Write or Set Block/Permanent
1 = V
0 = V
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#
0 = Unlock
7
STATUS (ECBLBS)
Lock-Bits
Block Lock-Bits
STATUS (WBWSLBS)
Lock-Bit
Lock-Bit
(WBWSS)
Lock Detected, Operation Abort
CCW
CCW
CCW
Low Detect, Operation Abort
OK
STATUS (VCCWS)
BESS
6
ECBLBS
5
Table 6. Status Register Definition
WBWSLBS
4
Check RY/BY# or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of V
level. The WSM interrogates and indicates the V
only after Block Erase, Full Chip Erase, Word/Byte Write or
Lock-Bit Configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when
V
SR.1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or WP# is V
the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
CCW
VCCWS
3
≠V
CCWH1/2
WBWSS
.
2
NOTES:
DPS
1
IL
. Reading
CCW
CCW
Rev. 1.27
R
0
level