LH28F800BJHE-PBTLT9 Sharp Microelectronics, LH28F800BJHE-PBTLT9 Datasheet - Page 43

• Manufacturer Part Number: LH28F800BJHE-PBTLT9
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8 90ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F800BJHE-PBTLT9

• Package: 48TSOP
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

6.2.7 Reset Operations
NOTES:
1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,
2. A reset time, t
3. When the device power-up, holding RP# low minimum 100ns is required after V
t
t
t
PLPH
PLRZ
2VPH
Sym.
the reset will complete within 100ns.
valid. Refer to AC Characteristics - Read-Only Operations for t
has been in stable there.
RP# Pulse Low Time
RP# Low to Reset during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-Bit Configuration
V
CC
2.7V to RP# High
PHQV
RY/BY#(R)
RY/BY#(R)
RP#(P)
RP#(P)
RP#(P)
(SR.7)
(SR.7)
V
CC
, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are
High Z
High Z
("0")
("0")
2.7V
("1")
V
("1")
V
V
V
V
V
V
V
V
OL
OL
IH
IH
IH
IL
IL
IL
IL
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration
Parameter
Figure 20. AC Waveform for Reset Operation
t
t
PLPH
PLPH
Reset AC Specifications
(A)Reset During Read Array Mode
t
2VPH
t
PLRZ
(C)RP# rising Timing
PHQV
.
Notes
1,2
2,3
2
CC
has been in predefined range and also
Min.
100
100
Max.
30
Rev. 1.27
Unit
ns
µs
ns