DA28F640J5-150 Intel, DA28F640J5-150 Datasheet - Page 44

• Manufacturer Part Number: DA28F640J5-150
• Description: Flash Mem Parallel 5V 64M-Bit 8M x 8/4M x 16 150ns 56-Pin SSOP
• Manufacturer: Intel

Specifications of DA28F640J5-150

• Package: 56SSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 5 V
• Sector Size: 128KByte x 64
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
6.4
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
44
V
V
V
V
V
V
V
V
V
Sym
IL
IH
OL
OH1
OH2
PENLK
PENH
LKO
HH
All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.
I
current draw is I
Includes STS.
Block erases, programming, and lock-bit configurations are inhibited when V
range between V
CMOS inputs are either V
Add 5 mA for V
Sampled, not 100% tested.
Block erases, programming, and lock-bit configurations are inhibited when V
between V
Master lock-bit set operations are inhibited when RP# = V
master lock-bit is set and RP# = V
is set and RP# = V
attempted with V
Tie V
RP# connection to a V
CCES
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
V
Normal Operations
V
Erase, Program, or
Lock-Bit Operations
V
RP# Unlock Voltage
DC Characteristics
PEN
PEN
PEN
CC
is specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s
Lockout Voltage
to V
Lockout during
during Block
LKO
Parameter
CC
(max) and V
CCQ
CCR
(4.5 V–5.5 V).
IH
PENLK
IH
< RP# < V
= V
or I
. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
HH
(max) and V
CCQ2
CCW
supply is allowed for a maximum cumulative period of 80 hours.
CC
CC
.
min.
± 0.2 V or GND ± 0.2 V. TTL inputs are either V
(min), and above V
HH
.
Notes
4,7,11
4,11
9,10
3,7
3,7
3,7
IH
(Continued)
7
7
8
PENH
. Block erases and programming are inhibited when the corresponding block-lock bit
(min), and above V
V
V
–0.5
0.85
–0.4
3.25
11.4
Min
2.0
2.4
3.6
4.5
CCQ
CCQ
CC
+ 0.5
(max).
Max
0.45
12.6
V
0.8
0.4
5.5
CC
IH
PENH
. Block lock-bit configuration operations are inhibited when the
Unit
V
V
V
V
V
V
V
V
V
V
V
(max).
V
I
V
I
V
I
V
I
V
I
Set master lock-bit
Override lock-bit
OL
OL
OH
OH
OH
ADVANCE INFORMATION
CCQ
CCQ
CCQ
CCQ
CCQ
= 5.8 mA
= 2 mA
= –2.5 mA (V
= –2.5 mA
= –100 µA
–2 mA (V
= V
= V
= V
= V
= V
PEN
CC
IL
or V
< V
CCQ1
CCQ2
CCQ1
CCQ1
CCQ1
V
IH
LKO
PENLK
.
Test Conditions
Min
Min
Min or V
Min or V
Min or V
, and not guaranteed in the range
CCQ2
CCQ1
, and not guaranteed in the
)
)
CCQ
CCQ
CCQ
= V
= V
= V
CCQ2
CCQ2
CCQ2
Min
Min
Min