CY37064VP44-100AI Cypress Semiconductor Corp, CY37064VP44-100AI Datasheet - Page 15

• Manufacturer Part Number: CY37064VP44-100AI
• Description: CPLD Ultra37000 Family 2K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37064VP44-100AI

• Package: 44TQFP
• Family Name: Ultra37000
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 12 ns
• Number Of User I/os: 37
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: -40 to 85 °C

Document #: 38-03007 Rev. *B
Inductance
Capacitance
Endurance Characteristics
3.3V Device Characteristics
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65 C to +150 C
Ambient Temperature with
Power Applied............................................. –55 C to +125 C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Operating Range
3.3V Device Electrical Characteristics
C
C
C
N
Commercial
Industrial
Military
V
V
V
V
I
I
I
I
Notes:
10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: V
L
IX
OZ
OS
BHL
9.
Parameter
Parameter
OH
OL
IH
IL
I/O
CLK
DP
Parameter
Dual pins are I/O with JTAG pins.
Parameter
[3]
[5]
Range
Maximum Pin
Inductance
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit Current
Input Bus-Hold LOW Sustaining
Current
[5]
Description
Minimum Reprogramming Cycles
[2]
Input/Output Capacitance
Clock Signal Capacitance
Dual Function Pins
Description
Description
V
at f = 1 MHz
Conditions
IN
Description
[5]
= 5.0V
Test
Ambient Temperature
–55°C to +125°C
[8, 5]
[9]
–40°C to +85°C
0°C to +70°C
TQFP
Lead
44-
Over the Operating Range
2
V
V
Guaranteed Input Logical HIGH Voltage for
all Inputs
Guaranteed Input Logical LOW Voltage for
all Inputs
V
V
Hold Disabled
V
V
CC
CC
I
O
CC
CC
Normal Programming Conditions
V
V
V
= GND OR V
PLCC
Lead
= GND or V
IN
IN
IN
44-
= Min.
= Min.
= Max., V
= Min., V
5
= 5.0V at f = 1 MHz at T
= 5.0V at f = 1 MHz at T
= 5.0V at f = 1 MHz at T
[2]
[7]
[7]
Test Conditions
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage............................................. 3.0 to 3.6V
Current into Outputs ...................................................... 8 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
CLCC
Lead
Test Conditions
Test Conditions
44-
IL
I
I
I
I
OUT
2
OH
OH
OL
OL
CC
CC
= 0.8V
Junction Temperature
= 8 mA (Com’l)
= 6 mA (Mil)
= –4 mA (Com’l)
= –3 mA (Mil)
, Output Disabled, Bus-
, Bus-Hold Disabled
= 0.5V
–40°C to +105°C
–55°C to +130°C
PLCC
Lead
0°C to +90°C
84-
8
[4]
A
A
A
CLCC
Lead
Ultra37000 CPLD Family
[4]
84-
= 25 C
= 25 C
= 25 C
5
[4]
[4]
[2]
TQFP
Lead
100-
8
1,000
Min.
Min.
–0.5
–10
–50
–30
+75
Max.
2.4
2.0
CC
10
12
16
TQFP
Lead
160-
is 3.3V± 0.16V.
9
10,000
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
Typ.
V
Max.
–160
CC
0.5
5.5
0.8
10
50
PQFP
Page 15 of 63
Lead
208-
[10]
11
Unit
Cycles
pF
pF
pF
Unit
Unit
mA
Unit
V
V
V
V
nH
A
A
A