CY37064VP44-100AI Cypress Semiconductor Corp, CY37064VP44-100AI Datasheet - Page 18

• Manufacturer Part Number: CY37064VP44-100AI
• Description: CPLD Ultra37000 Family 2K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37064VP44-100AI

• Package: 44TQFP
• Family Name: Ultra37000
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 12 ns
• Number Of User I/os: 37
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: -40 to 85 °C

Document #: 38-03007 Rev. *B
Switching Characteristics
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
Product Term Clocking Parameters
t
t
t
t
t
t
Pipelined Mode Parameters
t
Operating Frequency Parameters
f
f
f
f
Reset/Preset Parameters
t
t
t
t
t
t
User Option Parameters
t
t
t
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
COPT
SPT
HPT
ISPT
IHPT
CO2PT
ICS
MAX1
MAX2
MAX3
MAX4
RW
RR
RO
PW
PR
PO
LP
SLEW
3.3IO
[13]
[13]
[13]
[13]
[13, 14, 15]
[14, 15]
[13, 14, 15]
[13]
[13, 14, 15]
[13, 14, 15]
[13]
Parameter
[13]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clock (CLK
Set-Up Time from Input to Sync. Clk (CLK
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
Delay (Through Logic Array)
Output Synchronous Clock (CLK
Clock (CLK
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
CLK
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
CLK
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Input Register Synchronous Clock (CLK
Clock (CLK
Maximum Frequency with Internal Feedback (Lesser of 1/t
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
1/(t
Maximum Frequency with External Feedback (Lesser of 1/(t
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
or 1/t
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Output
Asynchronous Preset Width
Asynchronous Preset Recovery Time
Asynchronous Preset to Output
Low Power Adder
Slow Output Slew Rate Adder
3.3V I/O Mode Timing Adder
S
1
1
+ t
SCS
, CLK
, CLK
H
), or 1/t
)
[5]
2
2
0
0
, or CLK
, or CLK
, CLK
, CLK
Over the Operating Range
CO
1
1
)
, CLK
, CLK
[5]
3
3
) or Latch Enable
) or Latch Enable
2
2
0
, or CLK
, or CLK
, CLK
[5]
[5]
[5]
1
0
0
, CLK
, CLK
, CLK
3
3
) or Latch Enable (Through Logic Array)
)
[5]
[5]
2
[12]
1
1
, or CLK
[8]
0
, CLK
, CLK
, CLK
0
Description
(continued)
, CLK
2
2
, or CLK
1
, or CLK
, CLK
3
1
) or Latch Enable to Output
, CLK
2
, or CLK
CO
3
3
2
) or Latch Enable to Combinatorial Output
) or Latch Enable to Output Synchronous
, or CLK
+ t
SCS
CO
IS
), 1/t
, 1/(t
3
+ t
) to Output Register Synchronous
Ultra37000 CPLD Family
3
) or Latch Enable
S
ICS
S
) or 1/(t
+ t
, 1/(t
H
), or 1/t
WL
WL
+ t
+ t
CO
WH
WH
)
WL
[5]
), 1/(t
)
[5]
+ t
IS
WH
Page 18 of 63
+ t
),
IH
0
),
,
0
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns