CY37064VP44-100AI Cypress Semiconductor Corp, CY37064VP44-100AI Datasheet - Page 5

• Manufacturer Part Number: CY37064VP44-100AI
• Description: CPLD Ultra37000 Family 2K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37064VP44-100AI

• Package: 44TQFP
• Family Name: Ultra37000
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 12 ns
• Number Of User I/os: 37
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: -40 to 85 °C

Document #: 38-03007 Rev. *B
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
V
“Understanding Bus-Hold - A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
CC
or GND. For more information, see the application note
Ultra37000 CPLD Family
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