CY7C025-25JI Cypress Semiconductor Corp, CY7C025-25JI Datasheet - Page 11

• Manufacturer Part Number: CY7C025-25JI
• Description: SRAM Chip Async Dual 5V 128K-Bit 8K x 16 25ns 84-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25JI

• Package: 84PLCC
• Timing Type: Asynchronous
• Density: 128 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 12 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 8K

Switching Waveforms
Timing Diagram of Semaphore Contention
Semaphore Read After Write Timing, Either Side
Notes:
32. CE = HIGH for the duration of the above timing (both write and read cycle).
33. I/O
34. Semaphores are reset (available to both ports) at cycle start.
35. If t
A
A
A
0R
0L
0
SPS
0R
SEM
SEM
–A
SEM
R/W
R/W
I/O
R/W
–A
–A
OE
= I/O
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
2
2L
2R
0
R
L
L
R
0L
= LOW (request semaphore); CE
t
SA
(continued)
VALID ADRESS
t
AW
R
= CE
WRITE CYCLE
t
t
PWE
SCE
t
L
SD
DATA
t
= HIGH.
MATCH
SPS
MATCH
[33, 34, 35]
t
IN
HA
VALID
[32]
t
HD
t
SWRD
11
t
SOP
t
SOP
READ CYCLE
t
AA
VALID ADRESS
t
DOE
t
ACE
DATA
OUT
CY7C024/0241
CY7C025/0251
VALID
t
OHA
7C024–19
7C024–20