CY7C025-25JI Cypress Semiconductor Corp, CY7C025-25JI Datasheet - Page 2

• Manufacturer Part Number: CY7C025-25JI
• Description: SRAM Chip Async Dual 5V 128K-Bit 8K x 16 25ns 84-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25JI

• Package: 84PLCC
• Timing Type: Asynchronous
• Density: 128 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 12 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 8K

Logic Block Diagram
v
Notes:
1.
2.
3.
BUSY is an output in master mode and an input in slave mode.
I/O
I/O
0
9
–I/O
–I/O
8
17
on the CY7C0241/0251.
(CY7C025/0251)
on the CY7C0241/0251.
I/O
I/O
CE
R/W
UB
8L
0L
OE
LB
L
– I/O
– I/O
L
BUSY
L
L
L
15L
7L
L
A
[2]
A
[3]
A
12L
[1]
11L
0L
R/W
SEM
INT
L
L
L
ADDRESS
DECODER
CE
OE
UB
LB
CONTROL
L
L
L
L
I/O
ARBITRATION
SEMAPHORE
2
INTERRUPT
MEMORY
ARRAY
M/S
CONTROL
I/O
LB
ADDRESS
DECODER
CE
OE
UB
R
R
R
R
INT
SEM
R/W
R
R
CY7C024/0241
CY7C025/0251
R
A
A
A
I/O
I/O
BUSY
12R
11R
0R
8R
0R
R/W
OE
–
(CY7C025/0251)
UB
–
LB
R
I/O
I/O
[1]
CE
R
R
R
R
15R
R
7R
[3]
[2]
7C024–1