CY7C025-25JI Cypress Semiconductor Corp, CY7C025-25JI Datasheet - Page 13

• Manufacturer Part Number: CY7C025-25JI
• Description: SRAM Chip Async Dual 5V 128K-Bit 8K x 16 25ns 84-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25JI

• Package: 84PLCC
• Timing Type: Asynchronous
• Density: 128 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 12 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 8K

Switching Waveforms
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First
Busy Timing Diagram No.1 (CE Arbitration)
CE
CE
Right Address Valid First:
Note:
37. If t
L
ADDRESS
ADDRESS
R
Valid First:
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
PS
BUSY
BUSY
BUSY
BUSY
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
CE
CE
CE
CE
L,R
L,R
R
R
R
L
R
L
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
[37]
t
t
BLA
BLA
[37]
ADDRESS MATCH
ADDRESS MATCH
t
t
BLC
BLC
13
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C024/0241
CY7C025/0251
7C024–25
7C024–26
7C024–23
7C024–24