ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet - Page 13

• Manufacturer Part Number: ISL5216KI-1
• Description: Digital Down Converter 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5216KI-1

• Package: 196BGA
• Operating Temperature: -40 to 85 °C

Back End Data Routing
Back End Section
One back-end processing section is provided per channel.
Each back end section consists of a filter compute engine, a
FIFO/timer for evenly spacing samples (important when
implementing interpolation filters and resamplers), an AGC
and a cartesian-to-polar coordinate conversion block. A
block diagram showing the major functional blocks and data
routing is shown above. The data input to the back end
section is through the filter compute engine. There are two
other inputs to the filter compute engine, they are a data
recirculation path for cascading filters and a magnitude and
dφ/dt feedback path for AM and FM filtering. There are seven
outputs from each back end processing section. These are I
and Q directly out of the filter compute engine (I2, Q2), I and
28 27
DESTINATION BIT MAP
(BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)
28
27
26, 25
24
23
22:18
26
25 24 23 22 21 20 19 18
FILTER PROCESSOR SEQUENCE STEP NUMBER
AGC LOOP GAIN SELECT (PATH 01 ONLY)
UPDATE AGC LOOP (PATH 01 ONLY)
PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH
STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE)
FEED MAG/PHASE BACK TO FILTER PROCESSOR
FROM
01 - - FIFO/AGC PATH TO I1 AND Q1
10 - - DIRECT OUT/CASCADE PATH TO I2 AND Q2
11 - - FIFO/AGC PATH TO I2 AND Q2
CIC
13
M
U
X
(4:0)
PATH 0
COMPUTE
ENGINE
FILTER
ISL5216
PATH 2
TIMER
FIFO/
Q passed through the FIFO and AGC multipliers (I1, Q1),
magnitude (MAG), phase (or dφ/dt), and the AGC gain
control value (GAIN). The I2/Q2 outputs are used when
cascading back end stages. The routing of signals within the
back end processing section is controlled by the filter
compute engine. The routing information is embedded in the
instruction bit fields used to define the digital filter being
implemented in the filter compute engine.
FILTER
LOOP
AGC
MULT
MUX
AGC
EXT AGC
GAIN
PATH 3
PATH 1
POLAR
CART
TO
SHIFT
d/dt
x1, x2
x4, x8
M
U
X
dphi/dt: Q
MAG: I
July 13, 2007
I2
Q2
I1
Q1
GAIN
I2
Q2
PHASE
FN6013.3
MAG