ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet - Page 39

• Manufacturer Part Number: ISL5216KI-1
• Description: Digital Down Converter 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5216KI-1

• Package: 196BGA
• Operating Temperature: -40 to 85 °C

N/A for WR
P(15:0)
P(31:0)
P(31:0)
P(31:0)
P(15:0)
for RD;
31:24
23:16
31:16
15:11
15:0
15:8
15:0
15:0
7:0
4:3
2:0
10
9
8
7
6
5
Writing to this location will sample the AGC loop filter output (forward gain value) to stabilize it for reading. The value is read from
this location after waiting the four clocks required for synchronization.
Loop gain 0, decay gain value (signal decay, increase gain) 31:28 = EEEE (exponent), 27:24 = MMMM (mantissa).
Loop gain 1, decay gain value 23:20 = EEEE (exponent), 19:16 = MMMM (mantissa).
Loop gain 0, attack gain value (signal arrival, decrease gain) 15:12 = EEEE (exponent), 11:8 = MMMM (mantissa).
Loop gain 1, attack gain value 7:4 = EEEE (exponent), 3:0 = MMMM (mantissa).
Upper gain limit. See AGC section.
Lower gain limit. See AGC section.
AGC threshold. Equals 1.64676 times the desired magnitude of the I1/Q1 output.
Set to zero.
μP AGC loop gain select.
Enable filter compute engine control of AGC loop gain. When this bit is set, bit 28 in the filter compute engine destination field selects
which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.
10:9
00
10
01
11
Mean/Median. This bit controls the settling mode of the AGC. Mean mode settles to the mean of the signal and settles asymptotically
to the final value. Median mode settles to the median and settles with a fixed step size. This mode settles faster and more predictably,
but will have more AM after settling.
1
0
dphi/dt strobe enable. Set this bit to 1 to get a dphi/dt output without having to feed back through the filter compute engine.
Unused. Set to zero.
PhaseOutputSel
1
0
DiscShift(1:0). Shifts the phase up 0-, 1-, 2-, or 3-bit positions, discarding the bits shifted off the top. This makes the phase modulo
360, 180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits.
DiscDelay(2:0). Sets the delay, in sample times, for the dφ/dt calculation.
000
111
FUNCTION
Loop Gain 1 (μP controlled)
Loop gain 0 (μP controlled)
Loop Gain controlled by filter compute engine
Loop 1 (μP override of filter compute engine)
Mean mode
Median mode
dφ/dt
Phase
1
8
TABLE 21. AGC LOOP ATTACK/DECAY GAIN VALUES REGISTER (IWA = *010h)
39
TABLE 24. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)
TABLE 20. AGC GAIN READ STROBE REGISTER (IWA = *00Fh)
TABLE 23. AGC THRESHOLD REGISTER (IWA = *012h)
TABLE 22. AGC GAIN LIMITS REGISTER (IWA = *011h)
ISL5216
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
July 13, 2007
FN6013.3