IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 20

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

PowerPC 750FL RISC Microprocessor
3.2 Clock ac Specifications
Table 3-7 provides the clock ac timing specifications as defined in Figure 3-1.
Table 3-7. Clock ac Timing Specifications
Figure 3-1. SYSCLK Input Timing Diagram
Electrical and Thermal Characteristics
Page 20 of 65
Notes:
(Timing Reference)
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
2. The SYSCLK slew rate applies between 0.4 V and 1.0 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. See Section 3.3 Spread Spectrum Clock Generator on page 21 for long term jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL relock time is the maximum amount of time
6. This is a statement of the capability of the 750FL I/O circuitry. Not all systems can run at the maximum SYSCLK frequency. Contact
7. See Table 3-2 Recommended Operating Conditions on page 17 for recommended operating conditions
VM
SYSCLK
frequency, processor (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Table 5-2 750FL Microprocessor PLL Configuration on page 40
for valid PLL_CFG[0:4] settings.
required for PLL lock after a stable V
applies when the PLL has been disabled and subsequently reenabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.
IBM PowerPC Application Engineering for more information on high-speed bus design.
Number
2, 3
SYSCLK
1
4
Processor frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall slew rate
SYSCLK duty cycle measured at 0.8 V
Measurement Reference Voltage for SYSCLK (all I/O voltages)
SYSCLK cycle-to-cycle jitter
Internal PLL relock time
4
1
DD
and SYSCLK are reached during the power-on reset sequence. This specification also
Characteristic
VM
4
1, 6, 7
VM
SYSCLK
- Midpoint Voltage for SYSCLK
CV
IL
CV
IH
2
Minimum Maximum
400
5.0
1.0
20
25
–
–
Value
0.65
±150
733
200
100
50
75
MHz
MHz
V/ns
Unit
ns
ps
μs
%
V
750flds60.fm.6.0
Preliminary
April 27, 2007
3
Notes
1, 6
4, 3
3
3
5