IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 52

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

Table 5-6. Input/Output Use (Sheet 2 of 4)
DH[0:31]
DL[0:31]
DP[0:7]
DRTRY
GBL
GND
HRESET
INT
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
MCP
OV
PLL_CFG[0:4]
PLL_RNG[0:1]
QACK
QREQ
RSRV
SMI
SRESET
Notes:
750FL Micropro-
1. Depends on the system design. The electrical characteristics of the 750FL microprocessor do not add additional constraints to the system design. Therefore, whatever is
2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable the correct operation of the debuggers. Logical AND gates must be placed between
3. The 750FL microprocessor provides protection from metastability on inputs through the use of a “keeper” circuit on specific inputs. See Section 5.5 Level Protection on
4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (keepers assure no metastability of
5. The 750FL microprocessor does not require external pullups on address and data lines. Control lines must be treated individually.
cessor Signal
DD
done with the net depends on the system requirements.
these signals and 750FL microprocessor. (See Figure 5-7 IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector on page 55.)
page 55 for a more detailed description.
inputs but do not guarantee a level).
Name
Active Level
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Input/Output
Input/Output
Input/Output
Input/Output
Output
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Transfer Attributes
Interrupt/Resets
Interrupt/Resets
Interrupt/Resets
Interrupt/Resets
Status/Control
Power Supply
Power Supply
Usage Group
Clock Control
Data Bus
Data Bus
Control
LSSD
LSSD
LSSD
Input/Output with
Pullup Resistors
Not enabled
Not enabled
Not enabled
Internal
Level Protect
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
As required
As required
Required
External
Resistor
5k Ω
5k Ω
5k Ω
Active driver
Active driver or pullup
Pullup/pulldown, as required
Pullup required to OV
Pullup required to OV
Active driver or pullup
Pullup/pulldown, as required
Pullup/pulldown, as required
Must be actively driven
Chip actively drives
No connect
Active driver or pullup
Comments
DD
DD
2, 3, 4, 5
2, 3, 4, 5
1, 3, 4
1, 3, 4
1, 3, 4
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
3, 4, 5
Notes
3, 4
3, 4
5
5
5