IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 40

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

PowerPC 750FL RISC Microprocessor
5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation
The dual PLLs on the 750FL microprocessor are configured by the PLL_CFG[0:4] and PLL_RNG[0:1]
signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal processor and
VCO frequency of operation. The 750FL microprocessor PLL range configuration, for dual PLL operation, is
shown in Table 5-1.
Table 5-1. PLL_RNG[0:1] Definitions for Dual PLL Operation
5.1.3 PLL Configuration
PLL_CFG (Table 5-2) must be set so that both SYSCLK and the core frequency are within the clock ac timing
specifications shown in Table 3-7 Clock ac Timing Specifications on page 20. In addition, the core frequency
must not exceed the limit specified in the part number, and the system must meet the required specifications.
Table 5-2. 750FL Microprocessor PLL Configuration (Sheet 1 of 2)
System Design Information
Page 40 of 65
Notes:
1. The 2×−2.5× processor to bus ratios are not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
3. In clock-off mode, no clocking occurs inside the 750FL microprocessor regardless of the SYSCLK input.
for 1:1 mode operation. This mode is intended for manufacturing use only.
The ac timing specifications given in the document do not apply in PLL-bypass mode.
Binary
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
PLL_RNG[0:1]
PLL_CFG [0:4]
00
10
01
11
Decimal
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
Processor to Bus Frequency Ratio (PBFR)
PLL Frequency Range
600 MHz and above
Below 600 MHz
Reserved
Reserved
PLL Bypass
PLL Bypass
2.5×
OFF
OFF
3.5×
4.5×
5.5×
6.5×
2×
3×
4×
5×
6×
7×
1
1
2
2
750flds60.fm.6.0
Preliminary
April 27, 2007