GS88036BGT-200 GSI TECHNOLOGY, GS88036BGT-200 Datasheet - Page 10

• Manufacturer Part Number: GS88036BGT-200
• Description: SRAM Chip Sync Quad 2.5V/3.3V 9M-Bit 256K x 36 6.5ns/3ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS88036BGT-200

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 9 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 18 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 4
• Number Of Words: 256K

Notes:
1.
2.
3.
Rev: 1.05 11/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B
that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
Simplified State Diagram
CW
10/24
W
CR
R
CR
R
Deselect
X
GS88018/32/36BT-333/300/250/200/150
R
CR
First Read
Burst Read
R
A
, B
B
R
, B
C
, B
D
CR
, BW, and GW) control inputs, and
X
X
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