GS88036BGT-200 GSI TECHNOLOGY, GS88036BGT-200 Datasheet - Page 9
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GS88036BGT-200
Manufacturer Part Number
GS88036BGT-200
Description
SRAM Chip Sync Quad 2.5V/3.3V 9M-Bit 256K x 36 6.5ns/3ns 100-Pin TQFP Tray
Manufacturer
GSI TECHNOLOGY
Datasheet
1.GS88036BGT-200.pdf
(24 pages)
Specifications of GS88036BGT-200
Package
100TQFP
Timing Type
Synchronous
Density
9 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
2.5|3.3 V
Address Bus Width
18 Bit
Number Of I/o Lines
36 Bit
Number Of Ports
4
Number Of Words
256K
Synchronous Truth Table
Rev: 1.05 11/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
X = Don’t Care, H = High, L = Low
E = T (True) if E
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Operation
2
= 1 and E
1
= E
Address
External
External
External
3
Current
Current
Current
Current
Used
None
None
None
None
None
= 0; E = F (False) if E
Next
Next
Next
Next
Diagram
State
Key
CW
CW
CR
CR
W
R
R
X
X
X
X
X
2
= 0 or E
9/24
E
H
X
H
X
H
X
H
X
H
L
L
L
L
L
L
L
1
1
= 1 or E
E
H
H
H
X
L
X
L
X
X
X
X
X
X
X
X
X
2
3
= 1
E
H
X
H
X
X
X
X
X
X
X
X
X
X
L
L
L
3
GS88018/32/36BT-333/300/250/200/150
ADSP ADSC
X
X
X
H
H
H
X
H
X
H
X
H
X
L
L
L
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
ADV
X
X
X
X
X
X
X
X
H
H
H
H
L
L
L
L
© 2002, GSI Technology
W
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
D
Q
Q
D
D
Q
Q
D
D
3