GS88036BGT-200 GSI TECHNOLOGY, GS88036BGT-200 Datasheet - Page 7

• Manufacturer Part Number: GS88036BGT-200
• Description: SRAM Chip Sync Quad 2.5V/3.3V 9M-Bit 256K x 36 6.5ns/3ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS88036BGT-200

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 9 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 18 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 4
• Number Of Words: 256K

Mode Pin Functions
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those this input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.05 11/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
10
00
01
11
00
01
10
11
Pin Name
7/24
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
3rd address
1st address
4th address
H or NC
L or NC
State
H
H
L
L
GS88018/32/36BT-333/300/250/200/150
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
11
00
01
DD
© 2002, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18