GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet - Page 11

• Manufacturer Part Number: GS832132E-133
• Description: SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS832132E-133

• Package: 165FBGA
• Timing Type: Synchronous
• Density: 32 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 20 Bit
• Number Of I/o Lines: 32 Bit
• Number Of Ports: 4
• Number Of Words: 1M

Notes:
1.
2.
3.
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
X
X
CW
First Write
Burst Write
W
Simplified State Diagram with G
W
CW
11/32
W
CR
R
CR
R
Deselect
X
GS832118/32/36E-250/225/200/166/150/133
CW
W
CW
W
R
CR
First Read
Burst Read
R
R
CR
X
X
© 2003, GSI Technology