GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet - Page 24

• Manufacturer Part Number: GS832132E-133
• Description: SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS832132E-133

• Package: 165FBGA
• Timing Type: Synchronous
• Density: 32 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 20 Bit
• Number Of I/o Lines: 32 Bit
• Number Of Ports: 4
• Number Of Words: 1M

SAMPLE/PRELOAD
EXTEST
IDCODE
SAMPLE-Z
RFU
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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