GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet - Page 7

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GS832132E-133

Manufacturer Part Number
GS832132E-133
Description
SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS832132E-133

Package
165FBGA
Timing Type
Synchronous
Density
32 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
2.5|3.3 V
Address Bus Width
20 Bit
Number Of I/o Lines
32 Bit
Number Of Ports
4
Number Of Words
1M
Mode Pin Functions
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
11
01
10
00
Name
10
11
00
01
LBO
Pin
ZZ
FT
11
00
01
10
H or NC
L or NC
State
H
H
L
L
7/32
Standby, I
I
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
nterleaved Burst Sequence
Flow Through
Linear Burst
Function
2nd address
3rd address
4th address
1st address
Pipeline
Active
GS832118/32/36E-250/225/200/166/150/133
DD
= I
SB
A[1:0] A[1:0] A[1:0] A[1:0]
01
00
10
11
01
00
11
10
10
11
00
01
© 2003, GSI Technology
11
10
01
00
BPR 1999.05.18

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