GS840E18AT-166 GSI TECHNOLOGY, GS840E18AT-166 Datasheet - Page 14

• Manufacturer Part Number: GS840E18AT-166
• Description: SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 8.5ns/3.5ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS840E18AT-166

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Number Of I/o Lines: 18 Bit
• Number Of Ports: 2
• Number Of Words: 256K

Notes:
1.
2.
3.
Rev: 1.12 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
The upper portion of the diagram assumes active use of only the Enable (E
and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
Simplified State Diagram
CW
14/31
W
CR
R
CR
R
Deselect
X
1,
E
GS840E18/32/36AT/B-190/180/166/150/100
2,
E
3
) and Write (B
R
CR
First Read
Burst Read
R
R
A
, B
B
, B
CR
C
X
, B
X
D
, BW and GW) control inputs
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