GS840E18AT-166 GSI TECHNOLOGY, GS840E18AT-166 Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/2/286/gsi_technology_sml.jpg)
GS840E18AT-166
Manufacturer Part Number
GS840E18AT-166
Description
SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 8.5ns/3.5ns 100-Pin TQFP Tray
Manufacturer
GSI TECHNOLOGY
Datasheet
1.GS840E18AT-166.pdf
(31 pages)
Specifications of GS840E18AT-166
Package
100TQFP
Timing Type
Synchronous
Density
4 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
3.3 V
Number Of I/o Lines
18 Bit
Number Of Ports
2
Number Of Words
256K
Rev: 1.12 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQa–DQd
A0–An
Ba–Bd
ADSC
ADSP
ADV
GW
BW
CK
E1
E2
E3
G
Begin
A
Read A
tS
tS
tS
tS
tS
tH
tH
tH
tH
tOE
Cont
tKH
tKH
tS
tS
E2 and E3 only sampled with ADSC
tH
tH
Q(A)
tKL
tKL
Cont
tKC
tKC
tH
tOHZ
Flow Through Mode Timing
D(B)
B
Write B
tS
tS
tS
tS
ADSC initiated read
tH
tH
tH
tH
22/31
C
Read C
tLZ
tKQ
Fixed High
Read C+1 Read C+2 Read C+3 Read C
GS840E18/32/36AT/B-190/180/166/150/100
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
© 1999, GSI Technology
Deselected with E1
Cont
Q(C)
tHZ
Deselect
tKQX