CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet
CS5396-KS
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CS5396-KS Summary of contents
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... The CS5396/97 are targeted for the highest perfor- mance professional audio systems requiring wide dynamic range, negligible distortion and low noise. ORDERING INFORMATION CS5396-KS CS5397-KS CDB5396/97 VCOM MCLKA ADCTL ...
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... SPI Mode ......................................................................................................... Mode .........................................................................................................19 Establishing the Chip Address in I ANALOG CONNECTIONS - ALL MODES .......................................................................19 GROUNDING AND POWER SUPPLY DECOUPLING - ALL MODES ............................20 DIGITAL FILTER PLOTS .................................................................................................21 REGISTER DESCRIPTION ...............................................................................................25 PIN DESCRIPTIONS .........................................................................................................31 Power Supply Connections .....................................................................................31 Analog Inputs...........................................................................................................31 Analog Outputs........................................................................................................32 Digital Inputs............................................................................................................32 2 CS5396 CS5397 2 C Mode ....................................................19 DS229PP2 ...
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... Digital Input Pin Definitions for Stand-Alone MODE ............................................... 32 Digital Pin Definitions for CONTROL-PORT MODE................................................ 33 Digital Outputs......................................................................................................... 33 Digital Inputs or Outputs.......................................................................................... 34 Miscellaneous ......................................................................................................... 34 PARAMETER DEFINITIONS............................................................................................. 35 ADDITIONAL INFORMATION........................................................................................... 36 PACKAGE DIMENSIONS ................................................................................................. 37 DS229PP2 CS5396 CS5397 3 ...
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... THD (following calibration) V (Note 2) Z Differential Common-mode CMRR CS5396 CS5397 Min Typ Max TBD TBD 120 - TBD 117 - TBD 120 - 114 - TBD TBD 117 ...
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... Min Typ 0.5542 - 117 - 34/Fs - 34/ 0.646 - 0.323 - 10/ (Note 3) - 1.8 (Note 3) 20 (Note CS5396 CS5397 CS5397 Max Min Typ Max 0.4604 0 - 0.3958 0.005 - - 0.005 63.45 0.4979 - 63.50 - 117 - - - - 34/ 34/ 0.0 0.375 0 - 0.375 0.188 0 - 0.188 0.015 - - 0.015 127.35 0.646 - 127.35 63.68 0.323 - 63 ...
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... DGND = 0V, All voltages with respect to ground.) Symbol Analog VA VL Logic VD Digital |VA - VD| (Note 6) |VA - VL| (Note 6) |VD - VL| (Note 6) (Note (Note (Note 5) V IND stg CS5396 CS5397 128X oversampling MCLK=24.576 MHz Max Min Typ Max Unit TBD - 160 TBD mA TBD - 125 TBD 3.5 - ...
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... CS5396 CS5397 Min Typ Max Units 4.75 5.0 5.25 V 4.75 5.0 5.25 V 4.75 5.0 5. 0.4 V -10 - +50 C Typ Max Units - 100 kHz - 1950 ...
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... S compatible 8 SCLK input LRCK input MSB MSB-1 SDATA SCLK to LRCK & SDATA - SLAVE mode SCLK input LRCK input t sdo MSB SDATA SCLK to LRCK & SDATA - SLAVE mode CS5396 CS5397 slr1 slr2 sclkh sclkl t lrdss MSB MSB-1 Serial Data Format, Left Justified ...
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... Notes: 7. Data must be held for sufficient time to bridge the transition time of CCLK. 8. For F < 1 MHz. SCK CS CCLK CDIN DS229PP2 = 20 pF) L Symbol f sck t csh t css t scl t sch t dsu t (Note (Note (Note css t scl t sch dsu t dh CS5396 CS5397 ( °C; VD ±5%; A Min Max Unit - 6 MHz 1.0 - µ 100 ns - 100 ns t csh 9 ...
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... CCLK pF) L Symbol (Note 9) f scl t buf t hdst t low t high t sust t (Note 10) hdd t sud susp Repeated t high t hdst sud t sust low hdd CS5396 CS5397 ( °C; VD ±5%; A Min Max - 100 4.7 - 4.0 - 4.7 - 4 250 - - 300 f 4.7 - Stop Start susp hdst t r ...
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... Right Analog Input - DS229PP2 0 VREF CDIN/DFS CCLK/SM VCOM AINL+ CS5396/7 A/D CONVERTER AINL- AINR+ AINR- AGND0 LGND DGND AGND1 AGND2 Figure 1. Typical Connection Diagram CS5396 CS5397 +5V Digital + 0 CS/PDN -Controller/ 18 Configuration 17 10 CAL 16 Audio SDATA1 Data 15 SDATA2 Processor 13 LRCK 14 Timing SCLK Logic 7 & ...
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... GENERAL DESCRIPTION The CS5396/ 24-bit, stereo A/D converter designed for stereo digital audio applications. The analog input channels are simultaneously sampled by separate, patented, 7th-order tri-level delta-sig- ma modulators at either 128 or 64 times the output sample rate ( 128 Fs) of the device. The resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (Fs 100 kHz ...
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... CS5396/97 is placed in the Slave mode with the slave/master pin, S/M, high. High Pass Filter - Stand-Alone Mode The CS5396/97 includes a high pass filter after the decimator to remove the DC offsets introduced by the analog buffer stage and the CS5396/97 analog modulator. The characteristics of this first-order high pass filter are outlined below, for Fs equal to 48 kHz ...
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... VREF capacitor to settle. This is required to minimize noise and distortion also advised that the CS5396/97 be calibrated after the device has reached thermal equilibrium, approximately 10 seconds, to maximize performance. Synchronization of Multiple Devices - ...
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... Fs and the cho- sen Oversampling Mode. Table 2 shows some common master clock frequencies. 64 vs. 128 Oversampling Modes The CS5396/97 can operate Oversampling Mode with a 256 master clock (MCLKA/ maximum sample rate of 100 kHz. The device can also operate in a 128 Oversampling Mode with a 512 master clock (MCLKA/D) where the maxi- mum kHz ...
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... Data Valid on Rising Edge of SCLK MCLK equal to 256x Compatible. 64x Oversampling Mode SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 512x SLAVE 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 512x Compatible. 128x Oversampling Mode. CS5396 CS5397 Right Right ...
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... Oversampling Mode and equal to 128 in the 128 Oversampling Mode. Other frequencies are possible but may degrade system performance due to interference effects. The CS5396/97 is placed in the Slave mode via the control register. Synchronization of Multiple Devices - Control Port Mode In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling ...
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... CS5396/97 analog modulator. The high pass filter can be defeated with the control register also possible to write to the left/right offset registers to establish a prede- termined offset. The characteristics of this first-order high pass fil- ter are outlined below for Fs equal to 48 kHz. The filter response scales linearly with sample rate ...
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... Figures 17 - 24. µC Interface Formats The device supports either SPI or I mats. The CS5396/97 monitors the state of CS dur- ing power-up and will configure to an SPI interface if the pin is held low. Conversely, if the pin is held high, the port will configure ...
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... VREF and pin 3, AGND. The CDB5396/97 evaluation board dem- onstrates the optimum layout and power supply ar- rangements, as well as allowing fast evaluation of the ADC. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. CS5396 CS5397 DS229PP2 ...
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... DIGITAL FILTER PLOTS Figures 9-24 show the performance of the digital filters included in the ADC. All plots are normal- ized to Fs. Assuming a sample rate of 48 kHz, the Normalized Frequency (Fs) Figure 9. CS5396 Stop Band Attenuation Normalized Frequency (Fs) Figure 11. CS5396 Transition Band DS229PP2 CS5396 CS5397 ...
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... Normalized Frequency (Fs) Figure 13. CS5397 Stop Band Attenuation Normalized Frequency (Fs) Figure 15. CS5397 Transition Band 22 CS5396 CS5397 Normalized Frequency (Fs) Figure 14. CS5397 Passband Ripple Normalized Frequency (Fs) Figure 16. CS5397 Transition Band DS229PP2 ...
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... Stop Band Attenuation 64x Oversampling Mode Normalized Frequency (Fs) Figure 19. Low Group Delay Filter Transition Band 64x Oversampling Mode DS229PP2 CS5396 CS5397 Normalized Frequency (Fs) Figure 18. Low Group Delay Filter Passband Ripple 64x Oversampling Mode Normalized Frequency (Fs) Figure 20. Low Group Delay Filter Transition Band ...
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... Figure 21. Low Group Delay Filter Stop Band Attenuation 128x Oversampling Mode Figure 23. Low Group Delay Filter Transition Band 128x Oversampling Mode 24 CS5396 CS5397 Figure 22. Low Group Delay Filter Passband Ripple 128x Oversampling Mode Figure 24. Low Group Delay Filter Transition Band 128x Oversampling Mode ...
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... If this bit is set to ‘1’, the Left channel data from sdata1 source and sdata2 source (stored in Audio port register) will be sent out in SDATA1. SDATA2 will output all the Right channel data. DS229PP2 aapd adpd 1bit _LR/LL _hpen CS5396 CS5397 s/_m DFS mute ...
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... The LGD output will be the data at the serial audio port 1 if this bit is ‘1’ and all other bits of the port set to ‘0’. LGD(sdata2) Default = ‘1’ standard when DFS psycho psel18/_16 (sdata2 CS5396 CS5397 2 1 lgd lgd psel20/_16 (sdata1) (sdata2 DS229PP2 Out ...
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... Hold the SDATA1 pin of every chip to ‘1’ during power up. DS229PP2 fir1(LRCK) _psydither test mode. reserved for factory use only caddr4 caddr3 CS5396 CS5397 2 1 dstart1 dstart0 caddr2 caddr1 and SPI mode SPI buses and using chip address is nec caddr0 0 27 ...
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... Default = ‘0’. Input of psychoacoustic filter is taken from the sdata2 port. The 24-bit input data will be truncat psychoacoustic filter to the chosen output word length and then output to sdata1 of serial audio port hr/_bg 0 0 CS5396 CS5397 ddpd fir2in psychoin DS229PP2 ...
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... CS5396 CS5397 ralpha ralpha ralpha (bit2) (bit1) (bit0 ralpha ralpha ralpha (bit10) (bit9) (bit8 ralpha ralpha ralpha (bit18) (bit17) (bit16 lalpha lalpha lalpha (bit2) ...
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... CS5396 CS5397 pc8(bit2) pc8(bit1) pc8(bit0 pc7(bit2) pc7(bit1) pc7(bit0 pc6(bit2) pc6(bit1) pc6(bit0 pc5(bit2) pc5(bit1) pc5(bit0 pc4(bit2) pc4(bit1) pc4(bit0 pc3(bit2) pc3(bit1) pc3(bit0 pc2(bit2) pc2(bit1) pc2(bit0 ...
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... DGND - Digital Ground, Pin 12. Digital ground for the digital section. Analog Inputs AINR-, AINR+ - Differential Right Channel Analog Inputs, Pin 26, 27. Analog input connections for the right channel differential inputs. Nominally 4.0 Vpp differential for full-scale digital output. DS229PP2 CS5396 CS5397 31 ...
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... When high, the device enters power-down. Upon returning low, the device enters normal operation. Calibration of the device is required following release of power-down. 32 Oversampling Mode and 48 kHz in 128 x Oversampling Mode and 48 kHz in 128 compatible. The serial data format is left-justified when low. CS5396 CS5397 Oversampling x Oversampling x DS229PP2 ...
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... Control port data input and output for Chip Select Input, Pin 19. Control port chip select for SPI mode. The CS5396/97 monitors the state of CS during power- up and will configure to an SPI interface if this pin is held low. Conversely, if held high, the port will configure CCLK - Control Port Clock Input, Pin 17 ...
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... Fs. In slave mode, SCLK is an input which x x the output sample rate in the 64 x the output sample rate. A 128 x SCLK is preferred in the 64 x CS5396 CS5397 to 128 Fs ( the output sample rate in the 128 Oversampling Mode. x SCLK is preferred in the 128 x Oversampling Mode. The ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/ C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS229PP2 CS5396 CS5397 35 ...
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... Delta-Sigma A/D and D/A Converters” by Steven Harris. Presented at the 93rd Conven- tion of the Audio Engineering Society, October 1992. 36 CS5396 CS5397 5) “The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Convert- ers, and on Oversampling Delta Sigma ADCs” by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989 ...
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... PACKAGE DIMENSIONS DS229PP2 28 pin SOIC CS5396 CS5397 MILLIMETERS INCHES DIM MIN MAX MIN A 17.53 18.03 0.690 B 1.27 BSC 0.050 BSC C 7 NOM 7 NOM D 0.127 0.330 0.005 E 2.41 2.67 0.095 F 45 NOM 45 NOM NOM NOM H 0.203 0.381 0.008 7.42 7.59 0.292 K 8.76 9 ...
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... Optimal Noise Shaping, Journal of the Audio Engineering Society, Vol 40, No 7/8, 1992 July/Au- gust." The default coefficients in the CS5396 are the FIR 9-tap filter coefficients described in Table 3 of the paper. Since the effective noise shaping function is (1-H), the CS5396 registers save the (1-H) func- tion coefficients. Therefore, the negative of each filter coefficient is stored in the registers. Each coefficient is represented as a binary 2’ ...
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... Filter coefficient a6 (address 15h) Filter coefficient a7 (address 16h) Filter coefficient a8 (address 17h) Filter coefficient a9 (address 18h) Default 1101 1010 a2 - 0011 0101 a3 - 1100 0010 a4 - 0100 0011 a5 - 1100 1011 a6 - 0010 0011 a7 - 1110 1100 a8 - 0000 1001 a9 - 1111 1111 DS229PP2xC BIT 5 BIT 4 BIT 3 CS5396 CS5397 BIT 2 BIT 1 LSB 39 ...
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