CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 27

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

Test Mode 0(address 00000100)
aoverflow
doverflow
fir1_en(sdata)
fir1L_R(fir1 L channel enable)
_psydither(psychoacoustic filter dither disable)
dstart1, dstart2(dstart control bits)
Test Mode 1(add 00000101)
FOR FACTORY USE ONLY
Chip Address (address 00000110)
caddr(6-0) (chip address (bit6 to bit0))
DS229PP2
aoverflow
7
0
7
7
doverflow
caddr6
24-bit low-group-delay filter output will go through a high passfilter if “_hpen” bit in the Mode
register is ‘0’. If “_hpen” is ‘1’, data at the serial audio port will derive directly from the LGD filter
output.
If more than 1 bit is set for sdata2, low-group-delay filter output will be selected for output at the
port.
register.
the register.
Test purpose only.
Default = ‘0’.
Test purpose only.
Default = ‘0’.
A ‘0’ means adding dither in the psychoacoustic filter.
Default = ‘00’.
Test purpose only.
Default = ‘0000000’.
This is used to store the programmable chip address for I
When more than 1 device are connected to the I
essary, chip address set up is done by:
1) Hold the SDATA1 pin of every chip to ‘1’ during power up.
A ‘1’ indicates an overflow condition occurs in the modulator. This bit is reset by reading the
A ‘1’ indicates an overflow condition occurs in the decimation filter. This bit is reset by reading
Default = ‘0’.
6
0
6
6
0
fir1_en
caddr5
5
0
5
5
0
test mode. reserved for factory use only
fir1(LRCK)
caddr4
4
0
4
4
0
_psydither
caddr3
3
0
3
3
0
2
C or SPI buses and using chip address is nec-
caddr2
dstart1
2
2
0
2
2
0
C and SPI mode.
CS5396 CS5397
dstart0
caddr1
1
0
1
1
0
caddr0
0
0
0
0
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