CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 34

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

SDATA2 - Digital Audio Data Output #2, Pin 15.
Digital Inputs or Outputs
LRCK - Left/Right Clock, Pin 13.
SCLK - Serial Data Clock, Pin 14.
Miscellaneous
TSTO1, TSTO2 - Test Outputs, Pins 8 and 21.
34
Stand-Alone Mode - The 24-bit low group delay audio data is presented MSB first, in 2’s
complement format.
Control Port Mode - The 24-bit low group delay audio data is presented MSB first, in 2’s
complement format. The audio data can be followed by 8 peak detect bits which indicate the
peak signal level. The additional audio data options include; the standard 24-bit word; 16, 18,
or 20-bit data with or without psychoacoustically optimized dither. The SDATA2 output is
completely independent from SDATA1.
LRCK determines which channel, left or right, is to be output on SDATA1 and SDATA2. In
master mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an
input whose frequency must be equal to Fs. Although the outputs for each channel are
transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs.
Stand-Alone Mode - The relationship between LRCK, SCLK and SDATA is controlled by the
Digital Format Select (DFS) pin.
Control Port Mode - The relationship between LRCK, SCLK and SDATA is controlled by the
control register.
Stand-Alone Mode- Clocks the individual bits of the serial data from SDATA1 and SDATA2. In
master mode, SCLK is an output clock at 64
requires a continuously supplied clock at any frequency from 48
recommended). The relationship between LRCK, SCLK and SDATA is controlled by the
Digital Format Select (DFS) pin.
Control Port Mode - Clocks the individual bits of the serial data from SDATA1 and SDATA2.
In master mode, SCLK is an output clock at 128
Oversampling Mode and 64
In slave mode, SCLK is an input, which requires a continuously supplied clock at any
frequency from 32
Oversampling Mode and 64
relationship between LRCK, SCLK and SDATA is controlled by the control register.
These pins are intended for factory test outputs. They must not be connected to any external
component or any length of circuit trace.
x
to 128
x
x
the output sample rate in the 64
the output sample rate. A 128
x
SCLK is preferred in the 64
x
Fs. In slave mode, SCLK is an input which
x
the output sample rate in the 128
x
x
Oversampling Mode.
SCLK is preferred in the 128
x
Oversampling Mode. The
CS5396 CS5397
x
to 128
x
Fs (64
DS229PP2
x
is
x
x