LFSC3GA15E-6FN900C Lattice, LFSC3GA15E-6FN900C Datasheet - Page 18

• Manufacturer Part Number: LFSC3GA15E-6FN900C
• Description: IC FPGA 15.2KLUTS 900FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-6FN900C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-5. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output. A clock is required even in asynchro-
nous read mode.
The EBR memory supports two forms of write behavior for dual port operation:
1. Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current
2. Write Through — a copy of the input data appears at the output of the same port.
FIFO Configuration
The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out,
RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The
Full and Almost Full flags are registered with WCLK. The Empty and Almost Empty flags are registered with RCLK.
address) does not appear on the output.
Single Port
True Dual Port
Pseudo Dual Port
FIFO
Memory Mode
2-14
Configurations
16,384 x 1
16,384 x 1
16,384 x 1
16,384 x 1
1,024 x 18
1,024 x 18
1,024 x 18
1,024 x 18
8,192 x 2
4,096 x 4
2,048 x 9
8,192 x 2
4,096 x 4
2,048 x 9
8,192 x 2
4,096 x 4
2,048 x 9
512 x 36
8,192 x 2
4,096 x 4
2,048 x 9
512 x 36
512 x 36
LatticeSC/M Family Data Sheet
Architecture