LFSC3GA15E-6FN900C Lattice, LFSC3GA15E-6FN900C Datasheet - Page 37

• Manufacturer Part Number: LFSC3GA15E-6FN900C
• Description: IC FPGA 15.2KLUTS 900FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-6FN900C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many
multiple power supply and hot-swap applications. The maximum current during hot socketing is 4mA. See Hot
Socketing Specifications in Chapter 3 of this data sheet.
Power-Up Requirements
To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power sup-
plies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from VCC
and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional
requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no
restriction on the time between them. However, the ramp time for each must be 75 ms or less. Configuration of the
device will not proceed until the last power supply has reached its minimum operating voltage.
Additional Requirement for VCC and VCC12:
VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during power-
up and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the
same power supply.
Additional Requirement for VCCIO and VCCAUX:
If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is
powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses
through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual sourc-
ing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is unknown
and is likely to be in the hundreds of milliamps range).
Power-Down Requirements
To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or
VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed
monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as
VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power
supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition,
the power supplies can be removed in any order as long as they power down monotonically within 200ms of each
other.
Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must
not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and volt-
age regulators is not a concern here.
Note: The SERDES power supplies are NOT included in these requirements and have no specific sequencing
requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal
for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V
power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time.
The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here.
SERDES Power Supply Sequencing Requirements
When using the SERDES with 1.5V VDDIB or VDDOB supplies, the SERDES should not be left in a steady state
condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and the 1.5V power should be
applied to the SERDES at nominally the same time. The normal variation in ramp-up times of power supples and
voltage regulators is not a concern.
Additional Requirement for SERDES Power Supply
All VCC12 pins need to be connected on all devices independent of functionality used on the device. This analog
supply is used by both the RX and TX portions of the SERDES and is used to control the core SERDES logic
regardless of the SERDES being used in the design. VDDIB and VDDOB are used as supplies for the terminations
on the CML input and output buffers. If a particular channel is not used, these can be UNCONNECTED (floating).
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