LFSC3GA15E-6FN900C Lattice, LFSC3GA15E-6FN900C Datasheet - Page 70

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LFSC3GA15E-6FN900C

Manufacturer Part Number
LFSC3GA15E-6FN900C
Description
IC FPGA 15.2KLUTS 900FPBGA
Manufacturer
Lattice
Datasheet

Specifications of LFSC3GA15E-6FN900C

Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFSC3GA15E-6FN900C
Manufacturer:
LATTICE
Quantity:
101
Part Number:
LFSC3GA15E-6FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
sysCLOCK DLL Timing
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps.
IN
OUTOP
OUTOS
DUTY
DUTYRD
DUTYCIR
OPJIT
CPJIT
SKEW
LOCK
IDUTY
IPJIT
HI
LO
RSWD
FDEL
DLL
Parameter
1
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP)
Output Clock Frequency (CLKOS)
Output Clock Duty Cycle
Output Clock Duty Cycle
Output Clock Duty Cycle
Output Clock Period Jitter
Output Clock Cycle-to-Cycle Jitter
Output Clock to Clock Skew (Between
Two Outputs with the Same Phase
Setting)
DLL Lock-in Time
Input Clock Duty Cycle
Input Clock Period Jitter
Input Clock High Time
Input Clock Low Time
Reset Signal Pulse Width
Timeshift Delay Step Size
Delay Through the DLL when No Delay
Taps are Chosen but Not in Bypass
Mode.
Description
Over Recommended Operating Conditions
Output Clock Duty Cycle (at 50%
levels, 50% duty cycle input clock,
duty cycle correction turned off,
time reference delay mode)
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, time reference delay mode)
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, clock injection removal mode)
Applies to all operating conditions
At 80% level
At 20% level
3-26
Conditions
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
Min.
100
100
500
500
25
38
45
40
35
35
8
3
Typ.
760
45
+/- 250
18500
Max.
700
700
700
200
200
100
62
55
60
65
80
cycles
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ns
ps
%
%
%
%

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