P80C557E4EFB/01,51 NXP Semiconductors, P80C557E4EFB/01,51 Datasheet - Page 30

• Manufacturer Part Number: P80C557E4EFB/01,51
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,51

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-BQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 23. Description of S0CON bits
6.9.2
The SIO1 of the P8xC557E4 provides the fast-mode, which allows a
fourthfold increase of the bitrate up to 400 kHz. Nevertheless it is
downward compatible, i.e. it can be used in a 0 to 100 Kbit/s I
system.
Except from the bit rate selection (see Table 25) and the timing of
the SCL and SDA signals (see AC electrical characteristics in
section 11) the SIO circuit is the same as described in detail in the
80C51 Data Handbook IC20 for the 8xC552 microcontroller.
The I
data exchange. Features of the I
For more information on the I
fast-mode) please refer to the Philips publication number 9398 393
40011 and/or the 80C51 Data Handbook IC20.
1999 Mar 02
Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA)
Each device connected to the bus is software addressable by a
unique address
Masters can operate as Master-transmitter or as Master-receiver
It’s a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer
Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus
ICs can be added to or removed from an I
affecting any other circuit on the bus
Fault diagnostics and debugging are simple; malfunctions can be
immediately traced
Single-chip 8-bit microcontroller
2
C-bus is a simple bidirectional 2-wire bus for efficient inter-IC
SIO1 (I
SM0
0
0
1
1
2
C-bus Interface)
2
C-bus specification (including
SM1
0
1
0
1
2
C-bus are:
2
C-bus system without
MODE
0
1
2
3
2
C bus
Shift register
8-bit UART
9-bit UART
9-bit UART
30
P83C557E4/P80C557E4/P89C557E4
The on-chip I
I
they are:
The SI01 logic performs a byte oriented data transport, clock
generation, address recognition and bus control arbitration are all
controlled by hardware. Via two pins the external I
interfaced to the SIO1 logic:
SCL serial clock I/O and SDA serial data I/O, (see Special Function
Register bit S1CON.6/ENS1 for enabling the SIO1 logic).
The SIO1 logic handles byte transfer autonomously. It keeps track of
the serial transfers, and a status register (S1STA) reflects the status
of SIO1 and the I
Via the following four Special Function Registers the CPU interfaces
to the I
S1CON
S1STA
S1DAT
S1ADR
2
C-bus specification, supporting all I
Master transmitter
Master receiver
Slave transmitter
Slave receiver
DESCRIPTION
2
C logic.
2
C logic provides a serial interface that meets the
control register. Bit addressable by the CPU
status register whose contents may be used as a
vector to service routines.
data shift register. The data byte is stable as long
as S1CON.3/SI=1.
slave address register. It’s LSB enables/ disables
general call address recognition.
2
C-bus.
2
C-bus modes of operation,
f
variable
f
variable
CLK
CLK
/12
/64 or f
BAUD RATE
Product specification
CLK
2
C-bus is
/32